P87C51RA2FA,512 NXP Semiconductors, P87C51RA2FA,512 Datasheet - Page 32

• Manufacturer Part Number: P87C51RA2FA,512
• Description: Microcontrollers (MCU) 8B MCU 8K-64K/256-1K 2.7-5.5V 33MHZ
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C51RA2FA,512

• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: -
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details
• Other names: 935271890512

Philips Semiconductors
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output unless the CPU needs to perform an off-chip memory
access.
Reduced EMI Mode
AUXR (8EH)
AUXR.1
AUXR.0
See more detailed description in Figure 32.
Dual DPTR
The dual DPTR structure (see Figure 18) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
AUXR1 (A2H)
Where:
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
2003 Jan 24
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxxxx0B
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
80C51 8-bit microcontroller family
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
7
–
7
–
6
–
6
–
Select Reg
DPTR0
DPTR1
EXTRAM
AO
5
–
5
–
4
–
4
–
3
–
GF2
3
2
–
8KB/16KB/32KB/64KB OTP
2
0
DPS
0
1
EXTRAM
1
1
–
DPS
AO
0
0
32
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See Application Note AN458 for more details.
INC DPTR
MOV DPTR, #data16
MOV A, @ A+DPTR
MOVX A, @ DPTR
MOVX @ DPTR , A
JMP @ A + DPTR
AUXR1
DPS
BIT0
P87C51RA2/RB2/RC2/RD2
(83H)
DPH
Increments the data pointer by 1
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
Move ACC to external RAM (16-bit
address)
Jump indirect relative to DPTR
Figure 18.
(82H)
DPL
DPTR1
DPTR0
EXTERNAL
MEMORY
DATA
Product data
SU00745A