NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 284

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
Interrupt
Each SPI controller can generates an individual interrupt when data transfer is finished and the
respective interrupt event flag IF (SPI_CNTRL[16]) will be set. The interrupt event flag will
generates an interrupt to CPU if the interrupt enable bit IE (SPI_CNTRL[17]) is set. The interrupt
event flag IF can be cleared only by writing 1 to it.
In 3-WIRE mode, the interrupt flag in SLV_START_INTSTS will be set when the transfer has start
and there is also interrupt event when the received data meet the required bits which define in
TX_BIT_LEN and TX_NUM. If the received bits are less than the requirement and there is no
more serial clock input over the time period which is defined by the user in slave mode with no
slave select, the user can set the SLV_ABORT bit to force the current transfer done and then the
user can get a transfer done interrupt event.
Two Bit Transfer Mode
This SPI controller also supports two-bit transfer mode when set the TWOB bit (SPI_CNTRL[22])
to 1. When the TWOB bit is enabled, it can transmit and receives two-bit serial data
simultaneously.
For example, in master mode, the data stored at SPI_TX0 register and SPI_TX1 register will be
transmitted through the MOSIx0 pin and MOSIx1 pin respectively. In the meanwhile, the SPI_RX0
register and SPI_RX1 register will store the data received from MISOx0 pin and MISOx1 pin
respectively.
In slave mode, the data stored at SPI_TX0 register and SPI_TX1 register will be transmitted
through the MISOx0 pin and MISOx1 pin respectively. In the meanwhile, the SPI_RX0 register
and SPI_RX1 register will store the data received from MOSIx0 pin and MOSIx1 pin respectively.
Note that when enable the TWOB bit, the setting of TX_NUM must be programmed as 0x00 only.
Figure 5-58 Two Bits Transfer Mode (slave mode)
Publication Release Date: June 14, 2011
- 284 -
Revision V2.01