NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 9

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 5-62 SPI Timing in Slave Mode ........................................................................................ 288
Figure 5-63 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ......................................... 289
Figure 5-64 Timer Controller Block Diagram ............................................................................... 308
Figure 5-65 Clock Source of Timer Controller ............................................................................. 308
Figure 5-66 Continuous Counting Mode ...................................................................................... 310
Figure 5-67 Timing of Interrupt and Reset Signal ........................................................................ 325
Figure 5-68 Watchdog Timer Clock Control................................................................................. 326
Figure 5-69 Watchdog Timer Block Diagram............................................................................... 326
Figure 5-70 UART Clock Control Diagram................................................................................... 334
Figure 5-71 UART Block Diagram................................................................................................ 335
Figure 5-72 Auto Flow Control Block Diagram............................................................................. 336
Figure 5-73 IrDA Block Diagram .................................................................................................. 337
Figure 5-74 IrDA TX/RX Timing Diagram .................................................................................... 338
Figure 5-75 Structure of LIN Frame ............................................................................................. 339
Figure 5-76 Structure of RS-485 Frame ...................................................................................... 341
Figure 5-77 CAN Peripheral Block Diagram ................................................................................ 370
Figure 5-78 CAN Core in Silent Mode ......................................................................................... 372
Figure 5-79 CAN Core in Loop Back Mode ................................................................................. 373
Figure 5-80 CAN Core in Loop Back Mode Combined with Silent Mode .................................... 373
Figure 5-81 Data transfer between IFn Registers and Message ................................................. 376
Figure 5-82 Application Software Handling of a FIFO Buffer...................................................... 381
Figure 5-83 Bit Timing.................................................................................................................. 383
Figure 5-84 Propagation Time Segment...................................................................................... 385
Figure 5-85 Synchronization on “late” and “early” Edges ........................................................... 387
Figure 5-86 Filtering of Short Dominant Spikes........................................................................... 388
Figure 5-87 Structure of the CAN Core’s CAN Protocol Controller ........................................... 390
Figure 5-88 PS/2 Device Block Diagram ..................................................................................... 435
Figure 5-89 Data Format of Device-to-Host................................................................................. 437
Figure 5-90 Data Format of Host-to-Device................................................................................. 437
Figure 5-91 PS/2 Bit Data Format................................................................................................ 438
Figure 5-92 PS/2 Bus Timing ....................................................................................................... 438
Figure 5-93 PS/2 Data Format ..................................................................................................... 440
Figure 5-94 I
Figure 5-95 I
Figure 5-96 I
Figure 5-97 MSB Justified Timing Diagram (Format=1) .............................................................. 451
NuMicro™ NUC130/NUC140 Technical Reference Manual
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2
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S Clock Control Diagram........................................................................................ 450
S Controller Block Diagram .................................................................................... 450
S Bus Timing Diagram (Format =0) ....................................................................... 451
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Publication Release Date: June 14, 2011
Revision V2.01