NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 362

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NUC130VE3CN

Manufacturer Part Number
NUC130VE3CN
Description
IC MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130VE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130VE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130VE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
Time out Register (UA_TOR)
Register
UA_TOR
Bits
[31:16]
[15:8]
[7:0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Descriptions
Reserved
DLY
TOIC
Offset
UART0_BA+0x20 R/W
UART1_BA+0x20 R/W
UART2_BA+0x20 R/W
30
22
14
6
Reserved
TX Delay time value
This field is use to programming the transfer delay time between the last stop bit and
next start bit.
Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock = baud rate)
whenever the RX FIFO receives a new data word. Once the content of time out
counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a
receiver time out interrupt (INT_TOUT) is generated if UA_IER [RTO_IEN]. A new
incoming data word or RX FIFO empty clears INT_TOUT. In order to avoid receiver
time out interrupt generation immediately during one character is being received, TOIC
value should be set between 40 and 255. So, for example, if TOIC is set with 40, the
time out interrupt is generated after four characters are not received when 1 stop bit
and no parity check is set for UART transfer.
R/W
29
21
13
5
Description
UART0 Time Out Register
UART1 Time Out Register
UART2 Time Out Register
28
20
12
4
- 362 -
Reserved
Reserved
TOIC
DLY
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
25
17
9
1
Revision V2.01
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
24
16
8
0

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