IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 14

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

2
Note:
1. The pin number of the pins with the footnote ‘n’ is listed in order of channel (CH0 ~ CH16).
2. The content in the brackets indicates the position and the register name of the preceding bit. After the register name, if the punctuation ‘,...’ is followed, this bit is in a per-channel register.
If there is no punctuation following the address, this bit is in a global register or in a channel 0 only register. The addresses and details are included in Chapter 5 Programming Information.
3. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz in E1 mode.
Pin Description
IDT82P2816
(n=0~16)
(n=0~16)
RRINGn
TRINGn
RTIPn
Name
TTIPn
PIN DESCRIPTION
Output
Input
I / O
K4, M3, P4, T3, V4, V24, T23, P24,
J4, L3, N4, R3, U4, U24, R23, N24,
K1, M1, P1, T1, V1, V26, T26, P26,
J1, L1, N1, R1, U1, U26, R26, N26,
M23, K24, H23, F24, C24, D5, C3,
M26, K26, H26, F26, A24, A5, A3,
L23, J24, G23, E24, C23, D6, C4,
L26, J26, G26, E26, A23, A6, A4,
Pin No.
F4, H3
E4, G3
F1, H1
E1, G1
1
RTIPn / RRINGn: Receive Bipolar Tip/Ring for Channel 0 ~ 16
The receive line interface supports both Receive Differential mode and Receive Single Ended
mode.
In Receive Differential mode, the received signal is coupled into RTIPn and RRINGn via a 1:1
transformer or without a transformer (transformer-less).
In Receive Single Ended mode, RRINGn should be left open. The received signal is input on
RTIPn via a 2:1 (step down) transformer or without a transformer (transformer-less).
These pins will become High-Z globally or channel specific in the following conditions:
TTIPn / TRINGn: Transmit Bipolar Tip /Ring for Channel 0 ~ 16
The transmit line interface supports both Transmit Differential mode and Transmit Single
Ended mode.
In Transmit Differential mode, TTIPn outputs a positive differential pulse while TRINGn out-
puts a negative differential pulse. The pulses are coupled to the line side via a 1:2 (step up)
transformer or without a transformer (transformer-less).
In Transmit Single Ended mode, TRINGn should be left open (it is shorted to ground inter-
nally). The signal presented at TTIPn is output to the line side via a 1:2 (step up) transformer.
These pins will become High-Z globally or channel specific in the following conditions:
Refer to Section 3.3.8 Output High-Z on TTIP and TRING for details.
Line Interface
• Global High-Z:
• Per-channel High-Z
• Global High-Z:
• Per-channel High-Z
- Connecting the RIM pin to low;
- Loss of MCLK
- During and after power-on reset, hardware reset or global software reset;
- Receiver power down by writing ‘1’ to the R_OFF bit (b5, RCF0,...)
- Connecting the OE pin to low;
- Loss of MCLK;
- During and after power-on reset, hardware reset or global software reset;
- Writing ‘0’ to the OE bit (b6, TCF0,...)
- Loss of TCLKn in Transmit Single Rail NRZ Format mode or Transmit Dual Rail NRZ
- Transmitter power down by writing ‘1’ to the
- Per-channel software reset;
- The THZ_OC bit (b4, TCF0,...) is set to ‘1’ and the transmit driver over-current is
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Format mode, except that the channel is in Remote Loopback or transmit internal pat-
tern with XCLK
detected.
14
3
;
Description
2
;
T_OFF bit (b5, TCF0,...);
February 6, 2009