IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 18

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Pin Description
IDT82P2816
MCKSEL[0]
MCKSEL[1]
MCKSEL[2]
MCKSEL[3]
CLKT1
CLKE1
MCLK
Name
Output
Output
Input
Input
I / O
Pin No.
AC21
AD20
AF21
AE21
AD21
AD22
AC22
MCLK: Master Clock Input
MCLK provides a stable reference timing for the IDT82P2816. MCLK should be a clock with +/
-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK
is informed to the device by MCKSEL[3:0].
If MCLK misses (duty cycle is less than 30% for 10 µs) and then recovers, the device will be
reset automatically.
MCKSEL[3:0]: Master Clock Selection
These four pins inform the device of the clock frequency input on MCLK:
CLKT1: 8 KHz / T1 Clock Output
The output on CLKT1 can be enabled or disabled, as determined by the CLKT1_EN bit (b1,
CLKG).
When the output is enabled, CLKT1 outputs an 8 KHz or 1.544 MHz clock, as selected by the
CLKT1 bit (b0, CLKG). The output is locked to MCLK.
When the output is disabled, CLKT1 is in High-Z state.
CLKE1: 8 KHz / E1 Clock Output
The output on CLKE1 can be enabled or disabled, as determined by the CLKE1_EN bit (b3,
CLKG).
When the output is enabled, CLKE1 outputs an 8 KHz or 2.048 MHz clock, as selected by the
CLKE1 bit (b2, CLKG). The output is locked to MCLK.
When the output is disabled, CLKE1 is in High-Z state.
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Clock
18
Note:
0: GNDD
1: VDDIO
MCKSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
*
Description
Frequency (MHz)
1.544 X 2
1.544 X 3
1.544 X 4
1.544 X 5
1.544 X 6
1.544 X 7
1.544 X 8
2.048 X 2
2.048 X 3
2.048 X 4
2.048 X 5
2.048 X 6
2.048 X 7
2.048 X 8
1.544
2.048
February 6, 2009