DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet
DS3170N+
Specifications of DS3170N+
Related parts for DS3170N+
DS3170N+ Summary of contents
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... TEMP RANGE PIN-PACKAGE DS3170 0°C to +70°C 100 CSBGA DS3170+ 0°C to +70°C 100 CSBGA DS3170N -40°C to +85°C 100 CSBGA DS3170N+ -40°C to +85°C 100 CSBGA +Denotes a lead(Pb)-free/RoHS compliant package. FUNCTIONAL DIAGRAM DS3/ DS3/E3 E3 FRAMER/ DS3/E3 LINE LIU FORMATTER DS3170 Note: Some revisions of this device may incorporate deviations from published specifications known as errata ...
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DETAILED DESCRIPTION 2 BLOCK DIAGRAMS 3 APPLICATIONS 4 FEATURE DETAILS 4 .................................................................................................................................. 13 LOBAL EATURES 4.2 R DS3/E3 LIU F ECEIVE EATURES 4 ITTER TTENUATOR EATURES 4.4 R DS3/E3 F ECEIVE RAMER 4.5 T ...
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Line IO Pin Timing Source Selection ............................................................................................... 59 10.2.4 Clock Structures On Signal IO Pins ................................................................................................. 62 10.2.5 Gapped Clocks ............................................................................................................................... 63 10 ....................................................................................................................... 63 ESET AND OWER OWN 10 ............................................................................................................................... 66 LOBAL ESOURCES ...
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BERT .................................................................................................................................................. 108 10.11.1 General Description ...................................................................................................................... 108 10.11.2 Features ....................................................................................................................................... 108 10.11.3 Configuration and Monitoring ........................................................................................................ 108 10.11.4 Receive Pattern Detection ............................................................................................................. 109 10.11.5 Transmit Pattern Generation ......................................................................................................... 111 10.12 LIU – INE NTERFACE NIT ...
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RAMER ATA ATH 16 VERHEAD ORT HARACTERISTICS 16 ICRO NTERFACE HARACTERISTICS 16.3.1 SPI Bus Mode ............................................................................................................................... 217 16.3.2 Parallel Bus Mode ......................................................................................................................... 219 16.4 CLAD J ...
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Figure 2-1. LIU External Connections for the DS3/E3 Port of DS3170 .................................................................. 10 Figure 2-2. Block Diagram ................................................................................................................................... 11 Figure 3-1. DS3/E3 Line Card .............................................................................................................................. 12 Figure 7-1. DS3/E3 Framed LIU Mode ................................................................................................................. 19 Figure 7-2. DS3/E3 Unframed LIU Mode ...
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Figure 10-13. DS3 Frame Format ........................................................................................................................ 81 Figure 10-14. DS3 Subframe Framer State Diagram ............................................................................................ 81 Figure 10-15. DS3 Multiframe Framer State Diagram ........................................................................................... 82 Figure 10-16. G.751 E3 Frame Format ................................................................................................................. 89 Figure 10-17. G.832 E3 Frame Format ................................................................................................................. ...
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Table 5-1. Standards Compliance ........................................................................................................................ 16 Table 8-1. DS3170 Short Pin Descriptions ........................................................................................................... 25 Table 8-2. Detailed Pin Descriptions .................................................................................................................... 27 Table 9-1. Configuration of Port Register Settings ................................................................................................ 52 Table 10-1. LIU Enable Table .............................................................................................................................. 57 Table 10-2. All ...
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Table 12-19. FEAC Receive Side Register Map ................................................................................................. 165 Table 12-20. Transmit Side Trail Trace Register Map ......................................................................................... 168 Table 12-21. Trail Trace Receive Side Register Map .......................................................................................... 169 Table 12-22. Transmit DS3 Framer Register Map .............................................................................................. 174 Table 12-23. ...
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DETAILED DESCRIPTION The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or HDB3-coded AMI signal and ...
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Figure 2-2. Block Diagram DS3170 TPOS/TDAT TNEG TLCLK DS3/E3 TXP Transmit LIU TXN RPOS/RDAT RNEG/RCLV RLCLK DS3/E3 RXP Receive RXN LIU Clock Rate Adapter Serial Interface Mode: SPI (SCLK, MOSI, and MISO) TAIS TUA1 DS3 / E3 B3ZS/ Transmit HDB3 ...
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APPLICATIONS • Access Concentrators • Multiservice Access Platforms • ATM and Frame Relay Equipment • Routers and Switches • SONET/SDH ADM • SONET/SDH Muxes • PBXs • Digital Cross Connect • PDH Multiplexer/Demultiplexer • Test Equipment • Integrated Access ...
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FEATURE DETAILS The following sections describe the features provided by the DS3170 SCT. 4.1 Global Features Supports the following transmission formats: C-Bit DS3 M23 DS3 G.751 E3 G.832 E3 All controls and status fields are software accessible ...
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Transmit DS3/E3 Formatter Features Frame insertion for M23 and C-bit parity DS3, G.751 E3 and G.832 E3 B3ZS/HDB3 encoding Formatter pass-through mode for clear channel applications and externally defined frame formats Generation of RAI, AIS, ...
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Trail Trace Buffer Features Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register Insertion of the outgoing trail access point identifier from a 16-byte transmit register Receive trace identifier ...
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STANDARDS COMPLIANCE Table 5-1. Standards Compliance SPECIFICATION ANSI Digital Hierarchy – Electrical Interfaces T1.102-1993 T1.107-1995 Digital Hierarchy – Formats Specification T1.231-1997 Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring Network-to-Customer Installation – DS3 Metallic Interface Specification T1.404-1994 ...
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ACRONYMS AND GLOSSARY Definition of the terms used in this data sheet: • CCM—Clear-Channel Mode • CLAD—Clock Rate Adapter • Clear Channel—A Datastream with no framing included, also known as Unframed • FRM—Frame Mode • FSCT—Framer Single-Chip Transceiver Mode ...
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MAJOR OPERATIONAL MODES The major operational modes are determined by the FM[2:0] framer mode bits, as well as a few other control bits. Unused features are powered down and the data paths are held in reset. The configuration registers ...
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Figure 7-1. DS3/E3 Framed LIU Mode TPOS/TDAT TNEG TLCLK DS3/E3 TXP Transmit LIU TXN RPOS/RDAT RNEG/RCLV RLCLK DS3/E3 RXP Receive RXN LIU Clock Rate Adapter Serial Interface Mode: SPI (SCLK, MOSI, and MISO) TAIS TUA1 DS3 / E3 B3ZS/ Transmit ...
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DS3/E3 Unframed LIU Mode The frame mode determines the CLAD clock rate, LIU mode and selects B3ZS or HDB3. FRAME MODE FM[2:0] DS3 Unframed 100 E3 Unframed 110 LIU MODE LM[2:0] JA Off, B3ZS or HDB3 001 JA RX, ...
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DS3/E3 Framed POS/NEG Mode FRAME MODE FM[2:0] DS3 C-bit Framed 000 DS3 M23 Framed 001 E3 G.751 Framed 010 E3 G.832 Framed 011 LIU MODE LM[2:0] LIU Off, B3ZS or HDB3 000 LIU Off, AMI 000 Figure 7-3. DS3/E3 ...
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DS3/E3 Unframed POS/NEG Mode The frame mode determines the CLAD clock rate if used as the transmit clock and selects B3ZS or HDB3. FRAME MODE FM[2:0] DS3 Unframed 100 E3 Unframed 110 LIU MODE LM[2:0] LIU Off, B3ZS or ...
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DS3/E3 Framed UNI Mode FRAME MODE FM[2:0] DS3 C-bit Framed 000 DS3 M23 Framed 001 E3 G.751 Framed 010 E3 G.832 Framed 011 LIU MODE LM[2:0] Unipolar Mode 1XX Figure 7-5. DS3/E3 Framed UNI Mode TDAT TLCLK RDAT RLCV ...
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DS3/E3 Unframed UNI Mode The frame mode determines the CLAD clock rate if used as the transmit clock. FRAME MODE FM[2:0] DS3 Unframed 100 E3 Unframed 110 LIU MODE LM[2:0] Unipolar Mode 1XX Figure 7-6. DS3/E3 Unframed UNI Mode ...
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PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3170 Short Pin Descriptions Ipu (input with pullup), ...
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NAME PIN D[8] J8 D[7]/SPI_CPOL K8 D[6]/SPI_CPHA H7 D[5]/SPI_SWAP J7 D[4] K7 D[3] H6 D[2]/SPI_SCLK J6 D[1]/SPI_MOSI K9 D[0]SPI_MISO J5 H5, J4, H4, K3, A[8:1] J3, H3, K2, J2 A[0]/BSWAP K5 ALE RD/DS B2 WR/R/W C2 RDY ...
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NAME PIN AVDDJ E3 AVDDC G3 AVSSR B5 AVSST E4 AVSSJ D2 AVSSC G1 UNUSED UNUSED1 D6 UNUSED2 G2 8.2 Detailed Pin Descriptions Table 8-2. Detailed Pin Descriptions Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog ...
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PIN NAME TYPE TNEG O Transmit Negative AMI / Line OH Mask TNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the transmit line interface pins are enabled indicates that a negative pulse should be ...
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PIN NAME TYPE RPOS / Iad Receive Positive AMI / Data RDAT RPOS: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is disabled, a high on this pin indicates that a positive pulse ...
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PIN NAME TYPE TOHCLK O Transmit Overhead Clock TOHCLK: When the port framer is configured for one of the DS3 or E3 framing modes, this clock is used for the transmit overhead port signals TOH, TOHEN and TOHSOF. The TOHSOF ...
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PIN NAME TYPE TSOFI I Transmit Start Of Frame Input See Table 10-20. TSOFI: This signal can be used to align the start of the DS3 or E3 frames on the TSER pin to an external signal. In framed modes, ...
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PIN NAME TYPE TSOFO / O Framer Start Of Frame / Data Enable TDEN See Table 10-21. TSOFO: When the port framer is configured for the DS3 or E3 framed modes and the TSOFO pin function is selected, this signal ...
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PIN NAME TYPE positions of the data on the RSER pin. The signal goes high during each DS3/E3 payload bit and goes low during each DS3/E3 overhead bit. The signal is updated on the positive clock edge of the referenced ...
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PIN NAME TYPE address systems. When it is high the address is fed through the address latch to the internal logic. When it transitions to low, the address is latched and held internally until the signal goes back high. ALE ...
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PIN NAME TYPE GPIO7: This signal is configured general purpose IO pin. GPIO8 IO General Purpose IO 8 GPIO8: This signal is configured general purpose IO pin, or the PMU input signal. When configured ...
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PIN NAME TYPE AVSSR PWR Analog Ground for receive LIU AVSST PWR Analog Ground for transmit LIU AVSSJ PWR Analog Ground for jitter attenuator AVSSC PWR Analog Ground for CLAD DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION 36 of 230 ...
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Pin Functional Timing 8.3.1 Line IO 8.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing There is no suggested time alignment between the TXP, TXN and TX LINE signals and the TLCLK clock signal. The TX DATA signal is not a ...
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Figure 8-2. Tx Line IO HDB3 Functional Timing Diagram TLCLK (TX DATA) TPOS TNEG TXP BIAS V TXN (TX LINE) - 8.3.1.2 B3ZS/HDB3/AMI Mode Receive Pin Functional Timing There is no suggested time alignment between the RXP, ...
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Figure 8-4. Rx Line IO HDB3 Functional Timing Diagram RLCLK (RX DATA) RPOS RNEG RXP BIAS V RXN (RX LINE) - 8.3.1.3 UNI Mode Transmit Pin Functional Timing The TDAT pin is available when the line interface ...
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Figure 8-6. Rx Line IO UNI Functional Timing Diagram RLCLK RDAT RLVC INC BPV COUNTER TWICE 8.3.2 DS3/E3 Framing Overhead Functional Timing Figure 8-7 shows the relationship between the DS3 receive overhead port pins. Figure 8-7. DS3 Framing Receive Overhead ...
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Figure 8-10 shows the relationship between the DS3 transmit overhead port pins. Figure 8-10. DS3 Framing Transmit Overhead Port Timing TOHCLK TOHSOF TOHEN TOH F73 C73 F74 X1 F11 Figure 8-11 shows the relationship between ...
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Figure 8-13. DS3 Framed Mode Transmit Serial Interface Pin Timing TCLKO or TCLKI TSOFO TSOFI DS3 TGCLK DS3 TSER DS3 TDEN Figure 8-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing TCLKO or TCLKI ...
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Figure 8-16. DS3 Framed Mode Receive Serial Interface Pin Timing RCLKO or RCLKI RSOFO DS3 RGCLK DS3 RSER X1 DS3 RDEN Figure 8-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing RCLKO or RCLKI ...
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If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access. Additionally, CS may also be de-asserted between accesses when CPHA =1. In the case, any BURST access is ...
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Figure 8-23. SPI Serial Port Access For Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 SCK CS* MOSI 0 A13 A12 A11 A10 MSB MISO Figure 8-24. SPI Serial Port Access For Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ...
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Figure 8-27. 16-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 Figure 8-28. 16-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 ...
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Figure 8-29. 8-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address 0x2B0 = 0x34 0x2B1 = 012 Figure 8-30. 8-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address ...
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Figure 8-31. 16-Bit Mode without Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 0x2B2 = 0x5678 Figure 8-32. 16-Bit Mode with Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x3412 ...
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Figure 8-33. Clear Status Latched Register on Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 8-34. Clear Status Latched Register on Write A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 8-35 and Figure ...
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Figure 8-35. RDY Signal Functional Timing Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Figure 8-36. RDY Signal Functional Timing Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 16-8 and Figure See also ...
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INITIALIZATION AND CONFIGURATION STEP 1: Check Device ID Code. Before any testing can be done, the device ID code, which is stored in GL.IDR, shoud be checked against the device ID code shown below to ensure correct device is ...
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Table 9-1. Configuration of Port Register Settings PORT.CR1 MODE 0x040 DS3 C-Bit Framed 0x2000 DS3 M13 Framed 0x2000 E3.751 Framed 0x2000 E3.823 Framed 0x2000 Note: The Line Mode has been configured with the LIU enabled and the JA in the ...
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FUNCTIONAL DESCRIPTION 10.1 Processor Bus Interface 10.1.1 SPI Serial Port Mode The external processor bus can be configured to operate in SPI serial bus mode. See the section detailed timing diagrams. When SPI = 1, SPI bus mode is ...
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The clear on write mode expects the user to use the following protocol: 1. Read the latched status register 2. Write to the registers with the bits set that need to be cleared. This protocol is useful when multiple uncoordinated ...
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Figure 10-1. Interrupt Structure SRL bit SRIE bit SRL bit SRIE bit SRL bit SRIE bit BLOCK LATCHED STATUS and INTERRUPT ENABLE REGISTERS Figure 10-1 not only tells the user how to determine which event caused the interrupt, it also ...
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LIU Enabled, Loop Timing Enabled In this mode, the receive LIU sources the clock for both the receive and transmit logic. The RCLKO, TCLKO and TLCLK clock output pins will be the same. The transmit or receive line payload ...
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Sources of Clock Output Pin Signals The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks pin (TCLKI), the receive clock input pin (RLCLK), the recovered clock in the receive ...
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Table 10-3 identifies the source of the output signal TLCLK based on certain variables and register bits. Table 10-3. Source Selection of TLCLK Clock Signal LOOPT LBM[2:0] SIGNAL (PORT. (PORT.CR4) CR3) 1 XXX 1 XXX 0 010 0 110 0 ...
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Table 10-4. Source Selection of TCLKO (Internal Tx Clock) LOOPT LBM[2:0] SIGNAL PORT.CR3 (PORT.CR4 PLB (011) TCLKO 0 PLB (011) 0 PLB disabled 0 PLB disabled Figure 10-3 shows the source of the RCLKO signals. Figure 10-3. ...
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Transmit Line Interface Pins Timing Source Selection (TPOS/TDAT, TNEG) The transmit line interface signal pin group has the same functional timing clock source as the TLCLK pin described in Table 10-3. Other clock pins can be used for the ...
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Table 10-7. Transmit Framer Pin Signal Timing Source Select LBM[2:0] 1 XXX 1 XXX 1 XXX 0 PLB (011) or DLB (100) or ALB 001) 0 PLB (011) or DLB (100) 0 DLB & LLB (110) 0 LLB (010) 0 ...
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Table 10-9. Receive Framer Pin Signal Timing Source Select LBM[2:0] 1 XXX 1 XXX 1 XXX PLB (011) or DLB (100) or ALB 0 (001) 0 PLB (011) or DLB (100) 0 DLB&LLB (110) 0 LLB (010) 0 not LLB, ...
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Figure 10-4. Example IO Pin Clock Muxing TSER PIN INVERT TCLKI PIN INVERT RLCLK PIN INVERT RX LIU CLK CLAD CLOCKS DS3 CLK E3 CLK STS-1 CLK 10.2.5 Gapped Clocks The transmit and receive output clocks can be gapped in ...
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The processor bus output signals are also forced to be HIZ when the RST pin is active (low). The global reset bit (GL.CR1.RST) stays set after a one is written to it, but is reset to zero when ...
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Table 10-10. Reset and Power-Down Sources PIN REGISTER BITS ...
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Global Resources 10.4.1 Clock Rate Adapter (CLAD) The clock rate adapter is composed of a PLL block to create the internal clock which can be used for the transmit clock and/or LIU reference clock from a clock input on ...
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Table 10-12. Global 8 kHz Reference Source Table GL.CR2. GL.CR2. G8KIS G8KRS[1: None, the 8KHZ divider is disabled Derived from CLAD output clock 0 10 8KREF source selected by P8KRS[1: Undefined 1 XX GPIO4 ...
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General-Purpose IO Pins There are eight general-purpose IO pins that can be used for general IO, global signals and framer alarm signals. Each pin is independently configurable general-purpose input, general-purpose output, global signal or framer alarm. ...
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Table 10-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] 0000 X 0001 X 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 X 1100 1101 X 1110 1111 X X 10.4.5 Performance Monitor Counter Update Details The performance monitor ...
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Figure 10-7. Performance Monitor Update Logic PORT.CR1.PMUM PORT.CR1.PMU GL.CR1.GPMU 00 GPIO8(GPMU) PIN 01 1X ONE SEC GL.CR1.GPM 10.4.6 Transmit Manual Error Insertion Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register ...
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Figure 10-8. Transmit Error Insert Logic PORT.CR.MEIMS PORT.CR.TMEI GL.CR1.MEIMS 0 GL.CR1.TMEI GPIO6 PIN 1 (TMEI) 10.5 Port Resources 10.5.1 Loopbacks There are several loop back paths available. The following table lists the loopback modes available for analog loopback (ALB), line ...
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Figure 10-9 highlights where each loopback mode is located and gives an overall view of the various loopback paths available. Figure 10-9. Loopback Modes B3ZS/ DS3/E3 HDB3 Transmit Encoder LIU DS3/E3 B3ZS/ Receive HDB3 LIU Decoder Clock Rate Adapter 10.5.1.1 ...
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Line Loopback (LLB) Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and LLB are enabled at the same time when LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010. The clock from the receive ...
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The sequence will only work when the automatic AIS generation is not enabled. CV and P-bit errors can occur when AIS is automatically generated and can not be avoided. This sequence to generate an error free DS# AIS at the ...
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Table 10-18 lists the LAIS decodes for various line AIS enable modes. Table 10-18. Line AIS Enable Modes LAIS[1:0] FRAME MODE PORT.CR1 00 DS3 Any 10 DS3 Any Table 10-19 lists the PAIS decodes ...
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The generated BERT signal replaces the data on the TSER pin in framed modes when the BERT is enabled by setting the PORT.CR1.BENA. When the BERT is enabled The TDEN and RDEN pins will still be active but the ...
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Table 10-23. RSOFO/RDEN Output Pin Functions FM[2:0] RSOFOS PORT.CR2 PORT.CR3 0XX (FRM) 0 0XX (FRM) 1 1XX (UFRM) X Table 10-24. RCLKO/RGCLK Output Pin Functions FM[2:0] RCLKS PORT.CR2 PORT.CR3 0XX (FRM) 0 0XX (FRM) 1 1XX (UFRM) X 10.5.9 Framing ...
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Table 10-26. Line Mode Select Bits LM[2:0] LINE.TCR.TZSD & LM[2:0] LINE.RCR.RZSD (PORT.CR2) 0 000 0 001 0 010 0 011 1 000 1 001 1 010 1 011 X 1XX Line Code LIU B3ZS/HDB3 OFF B3ZS/HDB3 ON B3ZS/HDB3 ON B3ZS/HDB3 ...
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DS3/E3 Framer / Formatter 10.6.1 General Description The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates framing, inserts ...
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Arbitrary framing format support – Accepts a signal with an arbitrary framing format. The Line overhead/stuff periods are removed from the data stream using an overhead mask signal. • Detects alarms and errors – Detects DS3 alarm conditions (SEF, ...
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Figure 10-13. DS3 Frame Format ...
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The multiframe boundary is found by identifying the three multiframe alignment bits (M-bits). Since there are seven multiframe bits and three bits are required to identify the multiframe boundary checks may be needed to find the ...
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A Loss Of Frame (LOF) condition is declared by the LOF integration counter when it has been active for a total of T ms. The LOF integration counter is active (increments count) when an OOF condition is present ...
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FEBE errors (C-bit format only) are determined by the C-bits in subframe four (C indicates no error and any other value indicates an error. The receive alarm indication (RAI) bit will be set high in the transmitter when one or ...
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Table 10-27. C-Bit DS3 Frame Overhead Bit Definitions BIT DEFINITION Remote Defect Indication 1 2 (RDI Parity Bits and M Multiframe Alignment Bits Subframe ...
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The bits and C are all overwritten with the calculated payload parity from the previous DS3 frame The bits and C are all overwritten with the Far-End Block Error ...
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Receive C-bit DS3 Frame Format The DS3 frame format is shown in referred to as the far-end SEF/AIS bits). P are the multiframe alignment bits that define the multiframe boundary. F define the subframe boundary. Note: Both the M-bits ...
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Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off). The P-bits (P and ...
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Receive M23 DS3 Frame Format The DS3 frame format is shown in referred to as the far-end SEF/AIS bits). P are the multiframe alignment bits that define the multiframe boundary. F define the subframe boundary. Note: Both the M-bits ...
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Once all of the E3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame generation is disabled, the incoming E3 signal is passed on directly to error insertion. Frame generation is programmable (on ...
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A Change Of Frame Alignment (COFA) is declared when the G.751 E3 framer updates the data path frame counters with a frame alignment that is different from the current data path frame alignment. A Loss Of Signal (LOS) condition is ...
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Figure 10-17. G.832 E3 Frame Format FA1 FA2 Figure 10-18. MA Byte Format MSB 1 RDI REI SL SL RDI - Remote Defect Indicator REI - Remote Error Indicator SL - Signal Label MI - ...
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FA1 and FA2 are the Frame Alignment bytes the Error Monitoring byte used for path error monitoring the Trail Trace byte used for end-to-end connectivity verification the Maintenance and Adaptation byte used for far-end ...
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The type of BIP-8 error(s) inserted is programmable (errored BIP-8 bit, or errored BIP-8 byte). An errored BIP-8 bit is inverting a single bit error in the EM byte. An errored BIP-8 byte is inverting all eight bits in the ...
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A Change Of Frame Alignment (COFA) is declared when the G.832 E3 framer updates the data path frame counters with a frame alignment that is different from the current data path frame alignment. A Loss Of Signal (LOS) condition is ...
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Table 10-30. Payload Label Match Status EXPECTED RECEIVED 000 000 000 001 001 001 XXX XXX XXX XXX XXX and YYY equal any value other than 000 or 001; XXX The multiframe indicator and timing marker bits (sixth, seventh, and ...
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The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the order they are received, ...
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Transmit HDLC Overhead Processor The Transmit HDLC Overhead Processor accepts data from the Transmit FIFO, performs bit reordering, FCS processing, stuffing, packet abort sequence insertion, and inter-frame padding. A byte is read from the Transmit FIFO with a packet ...
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Any time there is less than 16 bits between two flags, the data will be discarded. Packet abort detection searches for ...
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The Trail Trace Controller extracts/inserts E3-G.832 trail access point identifiers using a 16-byte register(one for transmit, one for receive). The Trail Trace Controller demaps a 16-byte trail trace identifier from the E3-G.832 datastream in the receive direction and maps a ...
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However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This ...
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Figure 10-21. Trail Trace Byte (DT = Trail Trace Data) Bit 2 Bit 3 Bit 1 MSB DT[2] DT[3] MAS or DT[1] Trail trace extraction extracts the trail trace identifier from the incoming trail trace data stream, generates a trail ...
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The transmit direction inputs codewords from the microprocessor via the register interface and stores the codewords. It removes the codewords and performs FEAC processing. See FEAC Controller in the block diagram Figure 10-22. FEAC Controller Block Diagram TAIS TUA1 B3ZS/ ...
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In continuous mode, the code from TFCA[5:0] is inserted into a codeword, and sent until the mode is changed 10.9.3.3 Receive FEAC Processor The Receive FEAC Processor accepts an incoming ...
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Figure 10-24. Line Encoder/Decoder Block Diagram TAIS TUA1 B3ZS/ DS3/E3 HDB3 Transmit Encoder LIU DS3/E3 B3ZS/ Receive HDB3 LIU Decoder Clock Rate Adapter 10.10.2 Features • Performs bipolar to unipolar encoding and decoding – Converts a unipolar signal into an ...
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The third bipolar one is generated according to the normal AMI rules. When an EXZ error inserted, the Transmit Line Interface waits for the next occurrence of three (four) consecutive ...
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Figure 10-25. B3ZS Signatures RLCLK (RX DATA) RPOS RNEG RLCLK (RX DATA) V RPOS RNEG Figure 10-26. HDB3 Signatures RLCLK (RX DATA) RPOS RNEG RLCLK (RX DATA) RPOS V RNEG BPV detection checks the bipolar signal for bipolar violation (BPV) ...
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BERT 10.11.1 General Description The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random patterns with a generation polynomial of ...
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Table 10-31. Pseudo-Random Pattern Generation PATTERN TYPE PTF[4:0] (hex O.153 (511 type O.152 and O.153 08 (2047 type O.151 O.153 O.151 QRSS ...
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Synchronization is achieved if all 32 bits match the incoming pattern least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern resynchronization ...
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Figure 10-29. Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Pattern Matches 10.11.4.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An ...
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LIU – Line Interface Unit 10.12.1 General Description The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3 lines. The LIU has independent receive and transmit paths and a built-in ...
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Refer to LIU. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path disabled. The DS3/E3 LIU conforms to the telecommunications standards listed in external components ...
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Interfacing to the Line The transmitter interfaces to the outgoing DS3/E3 coaxial cable (75Ω) through a 2:1 step-down transformer connected to the TXP and TXN pins. recommended interface components. 10.12.4.4 Transmit Driver Monitor If the transmit driver monitor detects ...
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Table 10-34. Recommended Transformers MANUFACTURER PART Pulse Engineering PE-65968 Pulse Engineering PE-65969 TG07- Halo Electronics 0206NS TD07- Halo Electronics 0206NE Note: Table subject to change. Industrial temperature range and multiport transformers are also available. Contact the manufacturers for details at ...
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The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block. (24dB below ...
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OVERALL REGISTER MAP The register addresses of the global, test and the port are concatenated to cover the address range of 000 to 7FF. The address map requires 9 bits of address, ADR[8:0]. The register banks that are not ...
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Description Address offset 08C – 08F B3ZS/HDB3 transmit line encoder 090 – 09F B3ZS/HDB3 receive line decoder 0A0 – 0AF HDLC Transmit 0B0 – 0BF HDLC Receive 0C0 – 0CF FEAC Transmit 0D0 – 0DF FEAC Receive 0E0 – 0E7 ...
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REGISTER MAPS AND DESCRIPTIONS 12.1 Registers Bit Maps Note: In 8-bit mode, register bits[15:8] correspond to the upper byte, and register bits[7:0] correspond to the lower byte. For example, address 001h is the upper byte (bits [15:8]) and address ...
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Address Register Type Bit 7 16-bit 8-bit 040 040 PORT.CR1 RW 041 042 042 RW PORT.CR2 043 044 044 PORT.CR3 RW 045 046 046 RW PORT.CR4 047 048 048 UNUSED 049 04A 04A PORT.INV1 RW 04B 04C 04C PORT.INV2 RW ...
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Address Register Type Bit 7 16-bit 8-bit 074 074 BERT.RBECR1 R 075 076 076 R BERT.RBECR2 077 078 078 R BERT.RBCR1 079 07A 07A R BERT.RBCR2 07B 07C 07C- UNUSED 07E 07F Table 12-4. Line Register Bit Map Address Register ...
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Address Register Type Bit 7 16-bit 8-bit 0AA 0AA- UNUSED 0AE 0AF 0B0 0B0 RW HDLC.RCR 0B1 0B2 0B2 UNUSED 0B3 0B4 0B4 R HDLC.RSR 0B5 0B6 0B6 HDLC.RSRL RL 0B7 0B8 0B8 HDLC.RSRIE RW 0B9 0BA 0BA UNUSED 0BB ...
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Table 12-7. Trail Trace Register Bit Map Address Register Type Bit 7 16-bit 8-bit 0E8 0E8 RW TT.TCR 0E9 0EA 0EA R TT.TTIAR 0EB 0EC 0EC R TT.TIR 0ED 0EE 0EE UNUSED 0EF 0F0 0F0 TT.RCR RW 0F1 0F2 0F2 ...
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Address Register Type Bit 7 16-bit 8-bit 12A 12A T3.RSRL2 RL 12B 12C 12C RW T3.RSRIE1 12D 12E 12E RW T3.RSRIE2 12F 130- 130 RESERVED 132 133 134 134 T3.RFECR R 135 136 136 T3.RPECR R 137 138 138 T3.RFBECR ...
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Address Register Type Bit 7 16-bit 8-bit 136- 136- RESERVED 13A 13B 13C- 13C- UNUSED 13E 13F 12.1.5 E3 G.832 Register Bit Map Table 12-10. E3 G.832 Register Bit Map Address Register Type Bit 7 16-bit 8-bit 118 118 RW ...
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Global Registers Table 12-11. Global Register Map Address Register Register Description GL.IDR 000h Global ID Register 002h GL.CR1 Global Control Register 1 GL.CR2 004h Global Control Register 2 006h -- Unused 008h -- Unused 00Ah GL.GIOCR Global General Purpose ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- INTM Default 0 0 Bit # 7 6 Name TMEI MEIMS Default 0 0 Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits 11 to 10: Global 8KHz Reference Source [1:0] (G8KRS[1:0]). These bits determine the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name GPIO8S1 GPIO8S0 Default 0 0 Bit # 7 6 Name GPIO4S1 GPIO4S0 Default 0 0 Bits 15 to 14: General Purpose IO 8 Select [1:0] (GPIO8S[1:0]). These bits determine ...
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Bits General Purpose IO 1 Select [1:0] (GPIO1S[1:0]). These bits determine the function of the GPIO1 pin Input 01 = Port A status output selected by PORT.CR4:GPIOA[3:0] in port control registers 10 = Output logic ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 1 : CLAD Loss of Lock (CLOL) – This bit is set when any of the PLLs in the ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 2: One Second Interrupt Enable (ONESIE) This bit will drive the interrupt pin ...
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Port Register 12.3.1 Register Bit Descriptions Table 12-12. Port Register Map Address Register Register Description PORT.CR1 40h Port Control Register 1 0 42h PORT.CR2 Port Control Register 2 0 44h PORT.CR3 Port Control Register 3 0 PORT.CR4 46h Port ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name RESERVED PAIS2 Default 0 0 Bit # 7 6 Name TMEI MEIM Default 0 0 Bits 14 to 12: Payload AIS Select [2:0] (PAIS[2:0]). This bit controls when an ...
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Transmit BERT logic enabled Bit 7: Transmit Manual Error Insert (TMEI) This bit is used to insert errors in all error insertion logic configured to use this bit when PORT.CR1.MEIM=0. The error(s) will be inserted when this bit ...
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TXP and TXN driven 1 = TXP and TXN tri-stated Bit 13: Receive LIU Monitor Mode (RMON) This bit is used to enable the receive LIU monitor mode pre-amplifier. Enabling the pre-amplifier adds about linear ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name P8KRS1 P8KRS0 Default 0 0 Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the ...
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Bit 2: Receive Framer IO Signal Timing Select (RFTS). This bit controls the timing reference for the signals on the receive framer interface IO pins. The pins controlled are RSER, RSOFO / RDEN. See details Use output clocks ...
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Table 10-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] 0000 X 0001 X 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 X 1100 1101 X 1110 1111 ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name RESERVED RESERVED Default 0 0 Bit # 7 6 Name TOHI TOHCKI Default 0 0 Bit 12 : TSOFO / TDEN/ Invert (TSOFOI). This bit inverts the TSOFO / ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name TTSR FSR Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, ...
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Bit 1: Receive Loss Of Lock Status (RLOL) This bits indicates the status of the receive LIU clock recovery PLL circuit Locked to the incoming signal 1 = Not locked to the incoming signal Bit 0: Performance Monitoring ...
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Bit 1: Receive Loss Of Lock Latched Status Interrupt Enable (RLOLIE) The interrupt pin will be driven when this bit is enabled and the PORT.SRL.RLOLL bit is set and the bit in GL.ISRIE.PISRIE bit is enabled. Bit 0: Performance Monitoring ...
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BERT 12.4.1 BERT Register Map The BERT utilizes twelve registers. Table 12-13. BERT Register Map Address Register BERT.CR 060h BERT.PCR 062h 064h BERT.SPR1 066h BERT.SPR2 BERT.TEICR 068h 06Ah -- 06Ch BERT.SR BERT.SRL 06Eh BERT.SRIE 070h -- 072h BERT.RBECR1 074h ...
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Loading a new pattern will forces the receive pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note: QRSS, PTS, ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name BSP15 BSP14 Default 0 0 Bit # 7 6 Name BSP7 BSP6 Default 0 0 Bits BERT Seed/Pattern (BSP[15:0]) – Lower sixteen bits of 32 bits. ...
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TEIR[2:0] Error Rate 000 Disabled -1 001 1*10 -2 010 1*10 -3 011 1*10 -4 100 1*10 -5 101 1*10 -6 110 1*10 -7 111 1*10 Bit 2: Bit Error Insertion Enable (BEI) – When 0, single bit error insertion ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: Performance Monitoring Update Status Latched (PMSL) – This bit is set when the PMS bit transitions from 0 ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name BEC15 BEC14 Default 0 0 Bit # 7 6 Name BEC7 BEC6 Default 0 0 Bits Bit Error Count (BEC[15:0]) – Lower sixteen bits of 24 ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name BC15 BC14 Default 0 0 Bit # 7 6 Name BC7 BC6 Default 0 0 Bits Bit Count (BC[15:0]) – Lower sixteen bits of 32 bits. ...
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B3ZS/HDB3 Line Encoder/Decoder 12.5.1 Transmit Side Line Encoder/Decoder Register Map The transmit side utilizes one register. Table 12-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map Address Register 08Ch LINE.TCR 08Eh -- 12.5.1.1 Register Bit Descriptions Register Name: Register Description: ...
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Receive Side Line Encoder/Decoder Register Map The receive side utilizes six registers. Table 12-15. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map Address Register 090h LINE.RCR 092h -- 094h LINE.RSR 096h LINE.RSRL 098h LINE.RSRIE 09Ah -- 09Ch LINE.RBPVCR 09Eh LINE.REXZCR ...
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Bit 0: Receive Zero Suppression Decoding Disable (RZSD) – When 0, the B3ZS/HDB3 Decoder performs zero suppression (B3ZS or HDB3) and AMI decoding. When 1, zero suppression (B3ZS or HDB3) decoding is disabled, and only AMI decoding is performed. Register ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 5: Zero Suppression Code Detect Interrupt Enable (ZSCDIE) – This bit enables an ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name EXZ15 EXZ14 Default 0 0 Bit # 7 6 Name EXZ7 EXZ6 Default 0 0 Bits Excessive Zero Count (EXZ[15:0]) – These sixteen bits indicate the ...
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HDLC 12.6.1 HDLC Transmit Side Register Map The transmit side utilizes five registers. Table 12-16. Transmit Side HDLC Register Map Address Register 0A0h HDLC.TCR 0A2h HDLC.TFDR 0A4h HDLC.TSR 0A6h HDLC.TSRL 0A8h HDLC.TSRIE 0AAh -- 0ACh -- 0AEh -- 12.6.1.1 ...
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Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not an FCS is calculated and appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet. ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 5: Transmit FIFO Overflow Latched (TFOL) – This bit is set when a Transmit FIFO overflow condition occurs. Bit ...
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Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – This bit enables an interrupt if the TFFL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...
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Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is emptied, any ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name RFOIE -- Default 0 0 Bit 7: Receive FIFO Overflow Interrupt Enable (RFOIE) – This bit enables an interrupt ...
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Bits Receive Packet Status (RPS[2:0]) – These three bits indicate the status of the received packet and packet data. 000 = packet middle 001 = packet start. 010 = reserved 011 = reserved 100 = packet end: ...
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FEAC Controller 12.7.1 FEAC Transmit Side Register Map The transmit side utilizes five registers. Table 12-18. FEAC Transmit Side Register Map Address Register 0C0h FEAC.TCR 0C2h FEAC.TFDR 0C4h FEAC.TSR 0C6h FEAC.TSRL 0C8h FEAC.TSRIE 0CAh -- 0CCh -- 0CEh -- ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit FEAC Code B (TFCB[5:0]) – These six bits are ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE) – This bit enables an interrupt ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 3: Receive FEAC FIFO Empty (RFFE) – When 0, the Receive FIFO contains at least one code. When 1, ...
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Bit 1: Receive FEAC Codeword Detect Interrupt Enable (RFCDIE) – This bit enables an interrupt if the RFCDL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt ...
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Trail Trace 12.8.1 Trail Trace Transmit Side The transmit side utilizes three registers. Table 12-20. Transmit Side Trail Trace Register Map Address Register Register Description Trail Trace Transmit Control Register 0E8h TT.TCR Trail Trace Transmit Identifier Address Register 0EAh ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit Trail Trace Identifier Address (TTIA[3:0]) – These four bits ...
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Register Bit Descriptions Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 3: Receive Multiframe Alignment Disable (RMAD) – When 0, ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 2: Receive Trail Trace Identifier Mismatch (RTIM Received and expected trail trace identifiers match Received ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bit 3: Receive Trail Trace Identifier Change Interrupt Enable (RTICIE) – This bit enables ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name ETD7 ETD6 Default 0 0 Bits Expected Trail Trace Identifier Data (ETD[7:0]) – These eight bits ...
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DS3/E3 framer 12.9.1 Transmit DS3 The transmit DS3 utilizes two registers. Table 12-22. Transmit DS3 Framer Register Map Address Register Register Description T3 Transmit Control Register 118h T3.TCR T3 Transmit Error Insertion Register 11Ah T3.TEIR 11Ch -- Reserved 11Eh ...
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Bit 1: Transmit Frame Generation Disabled (TFGD) – Transmit Frame Generation is enabled 1 = Transmit Frame Generation is disabled; DS3 overhead positions in the incoming DS3 payload will be passed through to error insertion. Note: Frame generation ...
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Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit. When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is ...
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Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause ...
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Bit 10: Application Identification Channel (AIC) – This bit indicates the current state of the Application Identification Channel (AIC) from the C Bit 9: DS3 Idle Signal (IDLE) – When 0, the receive frame processor is not in a DS3 ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved Reserved Bit # 7 6 Name OOMFL SEFL Bit 11: T3 Framing Format Mismatch Latched (T3FML) – This bit is set when the T3FM bit transitions from zero ...
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Bit 2: Remote Error Indication Count Latched (FBECL) – This bit is set when the FBEC bit transitions from zero to one. This bit is set to zero in M23 DS3 mode. Bit 1: P-bit Parity Error Count Latched (PECL) ...
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Bit 3: Remote Defect Indication Interrupt Enable (RDIIE) – This bit enables an interrupt if the RDIL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...
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Bit 2: Far-End Block Error Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the FBECL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name FBE 15 FBE 14 Default 0 0 Bit # 7 6 Name FBE7 FBE6 Default 0 0 Bits Far-End Block Error Count (FBE[15:0]) – These sixteen ...
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Register Bit Descriptions Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved -- Default 0 0 Bit # 7 6 Name -- -- Default 0 0 Bits Transmit N Bit Control (TNBC[1:0]) – ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name Reserved Reserved Default 0 0 Bits Framing Error Insert Control (FEIC[1:0]) – These two bits control ...
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Receive G.751 E3 Register Map The receive G.751 E3 utilizes eight registers. Table 12-25. Receive G.751 E3 Framer Register Map Address Register 120h E3G751.RCR -- 122h E3G751.RSR1 124h 126h E3G751.RSR2 E3G751.RSRL1 128h E3G751.RSRL2 12Ah 12Ch E3G751.RSRIE1 12Eh E3G751.RSRIE2 -- ...
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Bits Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events that are counted count OOF occurrences (counted regardless of the setting of the ECC bit).. 01 = count ...
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Bit 1: Out Of Frame (OOF) – When 0, the receive frame processor is not in an out of frame (OOF) condition. When 1, the receive frame processor OOF condition. Bit 0: Loss Of Signal (LOS) – ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Bit # 7 6 Name -- -- Bit 8: Framing Error Latched (FEL) – This bit is set when a framing error is detected. Bit 0: Framing ...
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Bit 2: Alarm Indication Signal Interrupt Enable (AISIE) – This bit enables an interrupt if the AISL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...
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Transmit G.832 E3 Register Map The transmit G.832 E3 utilizes four registers. Table 12-26. Transmit G.832 E3 Framer Register Map Address Register 118h E3G832.TCR 11Ah E3G832.TEIR 11Ch E3G832.TMABR 11Eh E3G832.TNGBR 12.9.5.1 Register Bit Descriptions Register Name: Register Description: Register ...
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Transmit Frame Generation is disabled; E3 overhead positions in the incoming E3 payload will be passed through to error insertion. Note: The E3 overhead periods can still be overwritten by by error insertion, overhead insertion, or AIS generation. ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name -- -- Default 0 0 Bit # 7 6 Name TPT2 TPT1 Default 0 0 Bits Transmit Payload Type (TPT[2:0]) – These bits determines the value ...
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Receive G.832 E3 Register Map The receive G.832 E3 utilizes thirteen registers. Table 12-27. Receive G.832 E3 Framer Register Map Address Register 120h E3G832.RCR 122h E3G832.RMACR 124h E3G832.RSR1 126h E3G832.RSR2 128h E3G832.RSRL1 12Ah E3G832.RSRL2 12Ch E3G832.RSRIE1 12Eh E3G832.RSRIE2 130h ...
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Bits Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events that are counted count OOF occurrences (counted regardless of the setting of the ECC bit).. 01 = count ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved -- Bit # 7 6 Name Reserved Reserved Bit 12: Receive Payload Type Unstable (RPTU) – When 0, the receive payload type is stable. When 1, the receive ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved -- Bit # 7 6 Name GCL NRL Bit 13: Timing Source Indication Change Latched (TIL) – This bit is set when the TI[3:0] bits change state. Bit ...
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Register Name: Register Description: Register Address: Bit # 15 14 Name Reserved -- Default 0 0 Bit # 7 6 Name GCIE NRIE Default 0 0 Bit 13: Timing Indication Interrupt Enable (TIIE) – This bit enables an interrupt if ...
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Bit 3: Remote Defect Indication Interrupt Enable (RDIIE) – This bit enables an interrupt if the RDIL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...
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Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled ...