DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 37

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

8.3 Pin Functional Timing
8.3.1 Line IO
8.3.1.1
There is no suggested time alignment between the TXP, TXN and TX LINE signals and the TLCLK clock signal.
The TX DATA signal is not a readily available signal, it is meant to represent the data value of the other signals.
The TXP and TXN signals are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is enabled.
The TPOS, TNEG and TLCLK signals are only available when the line is in B3ZS/HDB3 or AMI mode and the
transmit line pins are enabled. The TPOS, TNEG and TLCLK pins can be enabled at the same as the LIU is
enabled.
The TPOS and TNEG signals change a small delay after the positive edge of the reference clock if the clock pin is
not inverted, otherwise they change after the negative edge. The TLCLK clock pin is the clock reference typically
used for the TPOS and TNEG signals, but they can be time referenced to the TCLKI, TCLKO, RLCLK or RCLKO
clock pins. The TPOS and TNEG pins can be inverted, but the polarity of TXP and TXN can not be inverted.
TXP and TXN are differential analog output pins. They are biased around ½ VDD and pulse above and below the
bias voltage by about 1 Volt. These signals are connected to the windings of a 1:2 step down transformer and the
other winding of the transformer creates the TX LINE signal. The TX LINE signal is a bipolar signal that pulses
about 1 Volt positive and 1 Volt negative above and below ground (0 volts). See
external connections.
Figure 8-1
Figure 8-1. Tx Line IO B3ZS Functional Timing Diagram
(TX DATA)
(TX LINE)
TLCLK
TNEG
TPOS
TXN
TXP
B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing
and
Figure 8-2
0 V
BIAS V
+
show the relationship between the analog and the digital outputs.
-
B
B
B
B
V
V
V
37 of 230
V
B3ZS CODEWORD
DS3170 DS3/E3 Single-Chip Transceiver
Figure 2-1
for a diagram of the