PEB20320H-V34 Infineon Technologies, PEB20320H-V34 Datasheet - Page 150

• Manufacturer Part Number: PEB20320H-V34
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34; PEB20320H-V34IN

User’s Manual
If an event leads to an interrupt with several bits set (e.g. FI and ERR) masking only a
proper subset of them (e.g. ERR) will lead to an interrupt with the nonmasked bits set
(e.g. FI). If all bits of an event are masked, the interrupt is suppressed. The interrupt
mask is therefore bit specific and not event specific.
NITBS: New ITBS value; if this bit is set the individual transmit buffer size ITBS is valid
Note: ITBS has to be set to ‘0’ if NITBS = ‘0’.
The bits RI, TI, TO, TA, TH, RO, RA are the so called channel command bits. They allow
the channel to be initialized, aborted or reconfigured at the serial side as well as at the
These bits can be decomposed in 3 independent command groups:
and
We will discuss these bits according to the groups.
1. Receive command group (6 commands)
– receive clear
– fast receive abort
P side.
RI = 0, RO = 0, RA = 0 (clears a previous receive abort or receive off condition, affects
only the serial interface)
The effect of this command depends on the previous history of the channel
• if the channel was never initialized by a receive initialization command it has no
• if it was initialized previously it clears a receive off or receive abort condition set by
• if no receive off or receive abort condition is set it has no effect.
RI = 0, RO = 0, RA = 1 (clears a previous receive abort or receive off condition, affects
only the DMA interface)
This abort is performed in the DMA controller and does not interfere with the reception
on the serial interface and the transfer of the data into the receive buffer. If this abort
is detected the current receive descriptor is suspended with an abort status (RA bit set
effect
a previous channel command
NITBS should be set to ‘0’ in conjunction with a transmit abort channel command.
and a new buffer field of TB is assigned to the channel. In this process first the
occupied buffer locations of the channel are released and then according to
ITBS a new buffer area is allocated. If there is not enough buffer size in TB
(occupied by other channels) the process will be aborted and an action request
failure interrupt is generated. After aborting no buffer size is allocated to the
channel. For preventing action request failure enough buffer locations must be
available. This can be done by reducing the buffer size of the other channels.
To avoid transmission errors all channels to be newly configured must be
deactivated before processing.
RI, RO, RA form the receive command group
TO, TI, TA the first transmit command group
TH
is the second transmit command group.
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Detailed Register Description
PEB 20320
01.2000