DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 113

IC TXRX QUAD T1/E1/J1 SCT 256BGA

DS21Q55

Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q55

Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

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18.
The DS21Q55 can implement the G.706 CRC-4 recalculation at intermediate path points. When this
mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe
alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This
change in data content is used to modify the CRC-4 checksum. This modification, however, does not
corrupt any error information the original CRC-4 checksum may contain. In this mode of operation,
TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the TSYNC
signal. If TSYNC is an input, then the user must assert TSYNC aligned at the beginning of the
multiframe relative to TSER. If TSYNC is an output, the user must multiframe-align the data presented to
TSER.
Figure 18-1. CRC-4 Recalculate Method
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)
TPOSO/TNEGO
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
+
CRC-4
CALCULATOR
113 of 237
XOR
NEW Sa BIT
DATA
MODIFY
Sa BIT
POSITIONS
TSER

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