DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet
DS21Q55
Specifications of DS21Q55
Available stocks
Related parts for DS21Q55
DS21Q55 Summary of contents
Page 1
... GENERAL DESCRIPTION The DS21Q55 is a quad software-selectable T1, E1 MCM device for short-haul and long-haul applications. Each port is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations ...
Page 2
MAIN FEATURES .........................................................................................................................9 1 UNCTIONAL ESCRIPTION 1 .................................................................................................14 LOCK IAGRAM 2. PIN FUNCTION DESCRIPTION ..................................................................................................18 2.1.1 Transmit Side.............................................................................................18 2.1.2 Receive Side..............................................................................................21 2 ARALLEL ONTROL ORT 2 XTENDED YSTEM NFORMATION ...
Page 3
T1 Operation ..............................................................................................80 12.1.2 E1 Operation..............................................................................................80 12 ATH ODE IOLATION 12.2.1 T1 Operation ..............................................................................................82 12.2.2 E1 Operation..............................................................................................82 12 RAMES UT OF YNC 12.3.1 T1 Operation ..............................................................................................83 12.3.2 E1 Operation..............................................................................................83 12.4 E-B C ...
Page 4
HDLC M ............................................................................................135 APPING 21.3.1 Receive ....................................................................................................135 21.3.2 Transmit ...................................................................................................137 21.3.3 FIFO Information ......................................................................................142 21.3.4 Receive Packet-Bytes Available ...............................................................142 21.3.5 HDLC FIFOs ............................................................................................143 21.4 R HDLC C ECEIVE ODE 21.5 L FDL S EGACY UPPORT 21.5.1 Overview ..................................................................................................144 21.5.2 ...
Page 5
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................198 30.1 D ................................................................................................198 ESCRIPTION 30 NSTRUCTION EGISTER SAMPLE/PRELOAD .............................................................................................202 BYPASS ...............................................................................................................202 EXTEST................................................................................................................202 CLAMP .................................................................................................................202 HIGHZ ..................................................................................................................202 IDCODE................................................................................................................202 30 ...........................................................................................203 EST EGISTERS 30 OUNDARY CAN ...
Page 6
... Figure 1-1. Block Diagram ..........................................................................................................................................14 Figure 1-2. Receive and Transmit LIU........................................................................................................................15 Figure 1-3. Receive and Transmit Framer/HDLC.......................................................................................................16 Figure 1-4. Backplane Interface..................................................................................................................................17 Figure 2-1. DS21Q55 PIN DIAGRAM, 27mm BGA ....................................................................................................35 Figure 5-1. Programming Sequence ..........................................................................................................................45 Figure 6-1. Clock Map ................................................................................................................................................49 Figure 14-1. Simplified Diagram of Receive Signaling Path.......................................................................................87 Figure 14-2 ...
Page 7
Figure 31-17. G.802 Timing, E1 Mode Only.............................................................................................................216 Figure 31-18. Transmit-Side Timing .........................................................................................................................216 Figure 31-19. Transmit-Side Boundary Timing (Elastic Store Disabled)..................................................................217 Figure 31-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ..........................217 Figure 31-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz ...
Page 8
Table 2-A. Pin Description Sorted by Pin Number .....................................................................................................29 Table 3-A. Register Map Sorted by Address ..............................................................................................................36 Table 7-A. T1 Alarm Criteria .......................................................................................................................................58 Table 8-A. E1 Sync/Resync Criteria ...........................................................................................................................60 Table 8-B. E1 Alarm Criteria.......................................................................................................................................65 Table 12-A. T1 Line Code Violation ...
Page 9
... MAIN FEATURES The DS21Q55 contains all the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features. General § Programmable output clocks for fractional T1, E1, H0, and H12 applications § Interleaving PCM bus operation § 8-bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola § ...
Page 10
Software or hardware based – Interrupt generated on change of signaling data – Receive signaling freeze on loss-of-sync, carrier loss, or frame slip § Addition of hardware pins to indicate carrier loss and signaling freeze § Automatic RAI generation ...
Page 11
... The DS21Q55 is compliant with the following standards: ANSI: T1.403-1995, T1.231–1993, T1.408 AT&T: TR54016, TR62411 ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4 Japanese: JTG ...
Page 12
... The DS21Q55 is a software-selectable quad MCM device for T1, E1 short-haul and long-haul applications. Each is composed of an LIU, framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single chip transceiver. The DS21Q55 is pin compatible with the DS21Qx5y family of products ...
Page 13
Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125ms frame there are 24 8-bit channels plus a framing bit assumed that the framing bit is sent first followed by channel ...
Page 14
... Block Diagram Figure 1-1 shows a simplified block diagram featuring the major components of the DS21Q55. Details are shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE. Figure 1-1. Block Diagram RRING RTIP TRING TTIP ...
Page 15
Figure 1-2. Receive and Transmit LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 15 of 237 RCL MUX JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
Page 16
Figure 1-3. Receive and Transmit Framer/HDLC RPOS RNEG RCLK TPOS TNEG TCLK REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 16 of 237 REC ...
Page 17
Figure 1-4. Backplane Interface DATA CLOCK SYNC SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 17 of 237 RLINK RLCLK RSIG RSIGFR RSYSCLK RSER RCLK ...
Page 18
PIN FUNCTION DESCRIPTION 2.1.1 Transmit Side Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from ...
Page 19
Signal Name: TLCLKx Signal Description: Transmit Link Clock Signal Type: Output Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock. Signal Name: TLINKx Signal Description: ...
Page 20
Signal Name: TPOSOx Signal Description: Transmit Positive-Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data by the output data format (IOCR1.0) ...
Page 21
Receive Side Signal Name: RLINKx Signal Description: Receive Link Data Signal Type: Output T1 Mode: Updated with either FDL data (ESF bits (D4 bits (ZBTSI) one RCLK before the start of a frame. E1 Mode: ...
Page 22
Signal Name: RFSYNCx Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNCx Signal Description: Receive Multiframe Sync Signal Type: Output An extracted ...
Page 23
Signal Name: RPOSOx Signal Description: Receive Positive-Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally connected to RPOSI. Signal Name: RNEGOx Signal Description: Receive Negative-Data ...
Page 24
... Signal Type: Input A dual function pin. A 0-to-1 transition issues a hardware reset to the DS21Q55 register set. A reset clears all configuration registers. Configuration register contents are set to 0. Leaving TSTRST high tri-states all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. ...
Page 25
... Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Section details. Signal Name: ESIBRDx Signal Description: Extended System Information Bus Read Signal Type: Input/Output Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Section details. for transceiver # 237 27 for more 27 for more ...
Page 26
JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This ...
Page 27
... A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the jitter attenuator for T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation, a 1.544MHz (50ppm) clock source can be used. ...
Page 28
Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should ...
Page 29
... Pinout The DS21Q55 is available in a 256-pin, 27mm, 1.27-pitch BGA package. Table 2-A. Pin Description Sorted by Pin Number NOTE: Signal is common to all transceivers unless otherwise stated. PIN NAME U3 A0 L17 A7/ALE (AS) M1 BPCLK1 H17 BPCLK2 F4 BPCLK3 V13 BPCLK4 P2 BTS P3 CS1 A14 ...
Page 30
PIN NAME TYPE P18 DVDD4 H3 DVSS1 U6 DVSS1 W8 DVSS1 A17 DVSS2 A20 DVSS2 B11 DVSS2 A5 DVSS3 B7 DVSS3 B9 DVSS3 H20 DVSS4 L20 DVSS4 N17 DVSS4 J4 ESIBRD1 C13 ESIBRD2 C3 ESIBRD3 U13 ESIBRD4 W6 ESIBS0_1 F18 ...
Page 31
PIN NAME TYPE E3 RCLK3 M18 RCLK4 M4 RCLKI1 A15 RCLKI2 A4 RCLKI3 R17 RCLKI4 M3 RCLKO1 C14 RCLKO2 B4 RCLKO3 T17 RCLKO4 N2 RD (DS) K4 RFSYNC1 D17 RFSYNC2 A2 RFSYNC3 V14 RFSYNC4 F1 RLCLK1 A12 RLCLK2 D3 RLCLK3 ...
Page 32
PIN NAME TYPE B2 RPOSI3 V15 RPOSI4 L4 RPOSO1 A16 RPOSO2 B1 RPOSO3 U15 RPOSO4 Y11 RRING1 Y14 RRING2 Y17 RRING3 Y20 RRING4 J2 RSER1 D15 RSER2 E2 RSER3 W17 RSER4 L2 RSIG1 B16 RSIG2 C1 RSIG3 Y18 RSIG4 K1 ...
Page 33
PIN NAME TYPE W19 RVSS4 W1 TCHBLK1 F20 TCHBLK2 C11 TCHBLK3 U20 TCHBLK4 V10 TCHCLK1 A18 TCHCLK2 B8 TCHCLK3 L18 TCHCLK4 Y9 TCLK1 B19 TCLK2 B10 TCLK3 M19 TCLK4 V6 TCLKI1 D19 TCLKI2 C8 TCLKI3 P20 TCLKI4 W7 TCLKO1 E18 ...
Page 34
PIN NAME TYPE Y2 TRING1 Y4 TRING2 Y6 TRING3 Y8 TRING4 W9 TSER1 C17 TSER2 C10 TSER3 K20 TSER4 W10 TSIG1 C18 TSIG2 A10 TSIG3 L19 TSIG4 W12 TSSYNC1 B18 TSSYNC2 D10 TSSYNC3 K19 TSSYNC4 U16 TSTRST V1 TSYNC1 D20 ...
Page 35
... Note: Locations C3, C13, J4, and U13 are used for the Extended System Information Bus (ESIB). These pin locations on the DS21Q352, DS21Q354, DS21Q552, and DS21Q554 are connected to ground. When replacing a DS21Qx5y with a DS21Q55B, these signals should be routed to control logic to gain access to the ESIB. If these pins remain connected to ground, the ESIB function will be disabled. ...
Page 36
... PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical Characteristics for more details ...
Page 37
ADDRESS 20 Status Register 6 21 Interrupt Mask Register 6 22 Status Register 7 23 Interrupt Mask Register 7 24 Status Register 8 25 Interrupt Mask Register 8 26 Status Register 9 27 Interrupt Mask Register 9 28 Per-Channel Pointer ...
Page 38
ADDRESS 4C Per-Channel Loopback Enable Register 2 4D Per-Channel Loopback Enable Register 3 4E Per-Channel Loopback Enable Register 4 4F Elastic Store Control Register 50 Transmit Signaling Register 1 51 Transmit Signaling Register 2 52 Transmit Signaling Register 3 53 ...
Page 39
ADDRESS 78 Line Interface Control 1 79 Line Interface Control 2 7A Line Interface Control 3 7B Line Interface Control 4 7C Test Register 7D Transmit Line Build-Out Control 7E Idle Array Address Register 7F Per-Channel Idle Code Value Register ...
Page 40
ADDRESS A4 HDLC #2 Receive Channel Select 3 A5 HDLC #2 Receive Channel Select 4 A6 HDLC #2 Receive Time Slot Bits/Sa Bits Select A7 HDLC #2 Transmit Channel Select 1 A8 HDLC #2 Transmit Channel Select 2 A9 HDLC ...
Page 41
ADDRESS D0 Transmit Align Frame Register D1 Transmit Nonalign Frame Register D2 Transmit Si Align Frame D3 Transmit Si Nonalign Frame D4 Transmit Remote Alarm Bits D5 Transmit Sa4 Bits D6 Transmit Sa5 Bits D7 Transmit Sa6 Bits D8 Transmit ...
Page 42
ADDRESS FC Reserved FD Reserved FE Reserved FF Reserved *TEST registers are used only by the factory. REGISTER NAME 42 of 237 REGISTER PAGE ABBREVIATION — — — — — — — — ...
Page 43
SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and per- channel data ...
Page 44
Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 Name — — Default CH8 CH7 Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah Bit # 7 6 Name — ...
Page 45
... PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting operation in the master mode register, enabling functions and enabling the common functions. The act of resetting the device automatically clears all configuration and status registers. ...
Page 46
... The DS21Q55 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the DS21Q55. The user can issue a chip reset at any time. Issuing a reset disrupts traffic flowing through the DS21Q55 until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register ...
Page 47
... The user always proceeds a read of any of the status registers with a write. The byte written to the register informs the DS21Q55 which bits the user wishes to read and have cleared. The user writes a byte to one of these registers, with the bit positions the user wishes to read and the bit positions the user does not wish to obtain the latest information on ...
Page 48
Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports ...
Page 49
... CLOCK MAP Figure 6-1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity ...
Page 50
... The T1 framer portion of the DS21Q55 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS21Q55 has been initialized, the control registers only need to be accessed when there is a change in the system configuration ...
Page 51
Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM bit 2 of all channels 1 ...
Page 52
Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 0/Transmit Yellow Alarm (TYEL not transmit yellow alarm 1 = transmit yellow alarm ...
Page 53
Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS stuffing occurs 1 = bit 7 forced ...
Page 54
Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 Name — — Default 0 0 Bit 0/Transmit Loop-Code Enable (TLOOP). See Section 0 = transmit data normally 1 = replace normal transmitted ...
Page 55
... AIS-CI and RAI-CI Generation and Detection The DS21Q55 can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI T1 ...
Page 56
T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. ...
Page 57
Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 Name RPDV TPDV Default 0 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. ...
Page 58
... Note 1: The definition of Blue Alarm (or AIS unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all- 1s signal. Blue Alarm criteria in the DS21Q55 has been set to achieve this performance recommended that the RBL bit be qualified with the RLOS bit. ...
Page 59
... E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS21Q55 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration ...
Page 60
Table 8-A. E1 Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS present in frame N and FAS FAS not present in frame Two valid MF alignment CRC4 words found within 8ms Valid MF ...
Page 61
Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 Name TFPT T16S Default 0 0 Bit 0/Transmit CRC4 Enable (TCRC4 CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable ...
Page 62
Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 Name Sa8S Sa7S Default 0 0 Bit 0/Automatic Remote Alarm Generation (ARA disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) ...
Page 63
Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
Page 64
E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words ...
Page 65
Table 8-B. E1 Alarm Criteria ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a RLOS resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 RCL 255 or 2048 ...
Page 66
COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF receive loss of ...
Page 67
Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 Name ID7 ID6 Default 1 0 Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to ...
Page 68
Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 Name RYELC RUA1C Default 0 0 Bit 0/Receive Loss-of-Sync Condition (RLOS interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit ...
Page 69
Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. ...
Page 70
Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
Page 71
Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to ...
Page 72
Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe ...
Page 73
I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 0/Output Data Format (ODF bipolar data at TPOSO and TNEGO ...
Page 74
Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM RSYSCLK is 1.544MHz RSYSCLK is 2.048MHz or ...
Page 75
LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 Name — — Default 0 0 Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the ...
Page 76
Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the device. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes ...
Page 77
Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is enabled, ...
Page 78
Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH17 to CH24 loopback ...
Page 79
ERROR COUNT REGISTERS The device contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration ...
Page 80
Line-Code Violation Count Register (LCVCR) 12.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is ...
Page 81
Register Name: LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits 0 to 7/Line-Code Violation Counter Bits (LCVC8 to LCVC15). LCV15 is the MSB ...
Page 82
Path Code Violation Count Register (PCVCR) 12.2.1 T1 Operation The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF ...
Page 83
Frames Out-of-Sync Count Register (FOSCR) 12.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame ...
Page 84
E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as ...
Page 85
DS0 MONITORING FUNCTION The device has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
Page 86
Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 Name — — Default 0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel ...
Page 87
... Change-of-State To avoid constant monitoring of the receive signaling registers, the DS21Q55 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1–RSCSE4 for E1 and RSCSE1–RSCSE3 for T1 are used to select which channels can cause a change-of-state indication ...
Page 88
Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
Page 89
Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 Name GRSRE — Default 0 0 Bit 0/Force Receive Signaling All Ones (FRSAO mode, this bit forces all signaling data at the RSIG ...
Page 90
Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
Page 91
Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
Page 92
Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive Signaling Change-of-State Interrupt Enable Register Address: 3Ch, 3Dh, 3Eh, 3Fh (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 CH30 Setting any of the CH1–CH30 bits in the RSCSE1–RSCSE4 registers ...
Page 93
Transmit Signaling Figure 14-2. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 14.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On ...
Page 94
E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
Page 95
Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B ...
Page 96
Register Name: TS1 to TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) CH2-A CH2-B CH2-C CH4-A CH4-B CH4-C CH6-A CH6-B CH6-C CH8-A CH8-B CH8-C CH10-A CH10-B CH10-C CH12-A CH12-B CH12-C CH14-A CH14-B ...
Page 97
Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 ...
Page 98
Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 Name CH22 CH21 Default 0 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx sourced from ...
Page 99
Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels frame. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h Bit # ...
Page 100
PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, ...
Page 101
Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
Page 102
Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 Name GRIC GTIC Default 0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed ...
Page 103
The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
Page 104
The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
Page 105
CHANNEL BLOCKING REGISTERS The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during ...
Page 106
Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Receive Channels Channel Blocking Control Bits (CH17 to CH24 ...
Page 107
Register Name: TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 Name CH8 CH7 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH1 to CH8 ...
Page 108
... ELASTIC STORES OPERATION The DS21Q55 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled independently of each other. Also, each elastic store can interface to either a 1 ...
Page 109
Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 Name TESALGN TESR Default 0 0 Bit 0/Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled ...
Page 110
Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 Name — — Default 0 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a ...
Page 111
Receive Side See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher ...
Page 112
T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 13, 17, 21, 25, and 29 (time slots ...
Page 113
... G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify the CRC-4 checksum ...
Page 114
... T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS21Q55 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 19.1 Transmit BOC Bits the TFDL register contain the BOC message to be transmitted. Setting BOCC causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position ...
Page 115
Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit # 7 6 Name — — Default 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits ...
Page 116
Register Name: SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a ...
Page 117
... ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) When operated in the E1 mode, the DS21Q55 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK and TLINK/TLCLK pins (Section 20.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (Section 20 ...
Page 118
Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
Page 119
Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
Page 120
Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with ...
Page 121
Register Name: RSiNAF Register Description: Received Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 Name SiF15 SiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (SiF1) Bit 1/Si Bit of Frame 3 (SiF3) Bit ...
Page 122
Register Name: RSa4 Register Description: Received Sa4 Bits Register Address: CBh Bit # 7 6 Name RSa4F15 RSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (RSa4F1) Bit 1/Sa4 Bit of Frame 3 (RSa4F3) Bit 2/Sa4 Bit of Frame ...
Page 123
Register Name: RSa6 Register Description: Received Sa6 Bits Register Address: CDh Bit # 7 6 Name RSa6F15 RSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (RSa6F1) Bit 1/Sa6 Bit of Frame 3 (RSa6F3) Bit 2/Sa6 Bit of Frame ...
Page 124
Register Name: RSa8 Register Description: Received Sa8 Bits Register Address: CFh Bit # 7 6 Name RSa8F15 RSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (RSa8F1) Bit 1/Sa8 Bit of Frame 3 (RSa8F3) Bit 2/Sa8 Bit of Frame ...
Page 125
Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 Name TSiF15 TSiF13 Default 0 0 Bit 0/Si Bit of Frame 1 (TSiF1) Bit 1/Si Bit of Frame 3 (TSiF3) Bit ...
Page 126
Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 Name TSa4F15 TSa4F13 Default 0 0 Bit 0/Sa4 Bit of Frame 1 (TSa4F1) Bit 1/Sa4 Bit of Frame 3 (TSa4F3) Bit 2/Sa4 Bit of Frame ...
Page 127
Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 Name TSa6F15 TSa6F13 Default 0 0 Bit 0/Sa6 Bit of Frame 1 (TSa6F1) Bit 1/Sa6 Bit of Frame 3 (TSa6F3) Bit 2/Sa6 Bit of Frame ...
Page 128
Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 Name TSa8F15 TSa8F13 Default 0 0 Bit 0/Sa8 Bit of Frame 1 (TSa8F1) Bit 1/Sa8 Bit of Frame 3 (TSa8F3) Bit 2/Sa8 Bit of Frame ...
Page 129
Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 ...
Page 130
HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte ...
Page 131
Table 21-A. HDLC Controller Registers REGISTER CONTROL AND CONFIGURATION H1TC, HDLC #1 Transmit Control Register H2TC, HDLC #2 Transmit Control Register H1RC, HDLC #1 Receive Control Register H2RC, HDLC #2 Receive Control Register H1FC, HDLC #1 FIFO Control Register H2FC, ...
Page 132
Register Name: H1TC, H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended ...
Page 133
Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 Name RHR RHMS Default 0 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD normal operation; ...
Page 134
FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
Page 135
HDLC Mapping 21.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. ...
Page 136
Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 Name RCB8SE RCB7SE Default 0 0 Bit 0/Receive ...
Page 137
Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table. Register Channels HxTCS1 1–8 HxTCS2 9–16 HxTCS3 17–24 HxTCS4 25–32 Register Name: H1TCS1, H1TCS2, H1TCS3, H1TCS4 ...
Page 138
Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 Name TCB8SE TCB7SE Default 0 0 Bit 0/Transmit ...
Page 139
Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the ...
Page 140
Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition ...
Page 141
Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time ...
Page 142
FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
Page 143
HDLC FIFOs Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 Name THD7 THD6 Default 0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). ...
Page 144
... Legacy FDL Support (T1 Mode) 21.5.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the DS21Q55 maintains the circuitry that existed in the previous generation of the T1 framer. In new applications recommended that the HDLC controllers and BOC controller described in Section 21.5.2 Receive Section In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register (RFDL). Because the RFDL is 8 bits in length, it fills up every 2ms (8 x 250µ ...
Page 145
Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. ...
Page 146
Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new ...
Page 147
... The DS21Q55 has the option of using software-selectable termination requiring only a single fixed pair of termination resistors. The DS21Q55’s LIU is designed to be fully software selectable for E1 and T1, requiring no change to any external resistors for the receive side. The receive side allows the user to configure the device for 75Ω, 100Ω ...
Page 148
... Monitor Mode Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry. The DS21Q55 can be programmed to support these applications through the monitor mode control bits MM1 and MM0 in the LIC3 register Figure 22-1. Typical Monitor Application ...
Page 149
... TCLK. Also, the waveforms created are independent of the duty cycle of TCLK. The transmitter in the DS21Q55 couples to the transmit twisted pair (or coaxial cable in some E1 applications) through a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used must meet the specifications listed in option of using software-selectable transmit termination ...
Page 150
... PLL. 22.5 Jitter Attenuator The DS21Q55 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the ...
Page 151
LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 Name L2 L1 Default 0 0 Bit 0/Transmit Power-Down (TPD powers down the transmitter and tri-states the TTIP ...
Page 152
T1 Mode DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft DSX-1 (266ft to 399ft DSX-1 (399ft to 533ft DSX-1 ...
Page 153
Register Name: TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 Name - AGCE Default 0 0 Bit 0–5 Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the ...
Page 154
Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 Name ETS LIRST Default 0 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit redefines the operation of the transmit ...
Page 155
Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 Name — TCES Default 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and ...
Page 156
Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 Name CMIE CMII Default 0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 RT0 Internal Receive-Termination Configuration 0 0 Internal receive-side termination disabled ...
Page 157
Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 Name BSYNC BD Default 0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 ...
Page 158
Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is ...
Page 159
Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling ...
Page 160
... Note 2: Resistors R should be set to 60Ω each if the internal receive-side termination feature is enabled. When this feature is disabled 37.5Ω for 75Ω coaxial E1 lines, 60Ω for 120Ω twisted-pair E1 lines, or 50Ω for 100Ω twisted-pair T1 lines. Note 1µF ceramic. DS21Q55 TTIP C ...
Page 161
... Note 7: The 68mF is used to keep the local power-plane potential within tolerance during a surge. VDD 0.1µ VDD 0.1µ 0.1µF 161 of 237 VDD DS21Q55 0.1µF 0.01µF TTIP DVDD DVSS 0.1µF 10µF TRING TVDD + TVSS 0.1µF 10µF RVDD + RVSS RTIP RRING 68µF ...
Page 162
Component Specifications Table 22-A. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
Page 163
Figure 22-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 22-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
Page 164
... Figure 22-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 22-8. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS21Q55 TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DS21Q55 TOLERANCE 1.5 MINIMUM TOLERANCE LEVEL AS PER ITU G.823 20 10 100 1k FREQUENCY (Hz) 164 of 237 10k 100k 0.2 2.4k 18k 10k 100k ...
Page 165
... Figure 22-9. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 22-10. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS21Q55 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS21Q55 E1 MODE 10 100 1K FREQUENCY (Hz) 165 of 237 TR 62411 (Dec. 90) Prohibited Area 10K 100K ITU G.7XX 10K 100K ...
Page 166
... PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21Q55 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TCD1 and TCD2) and selects the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register ...
Page 167
Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 Name TC1 TC0 Default 0 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 ...
Page 168
Register Name: TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 Name C7 C6 Default 0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. ...
Page 169
Register Name: RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A ...
Page 170
Register Name: RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A ...
Page 171
Register Name: RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 0 0 ...
Page 172
Register Name: RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A ...
Page 173
BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating and detecting the following patterns: § The pseudorandom patterns ...
Page 174
Figure 24-1. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 24-2. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO ...
Page 175
BERT Register Descriptions Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 Name TC TINV Default 0 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize ...
Page 176
Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 Name EIB2 EIB1 Default 0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is ...
Page 177
Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to ...
Page 178
Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
Page 179
BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
Page 180
BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO ...
Page 181
BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO ...
Page 182
Register Name: BIC Register Description: BERT Interface Control Register Register Address: EAh Bit # 7 6 Name — RFUS Default 0 0 Bit 0/BERT Enable (BERTEN BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR ...
Page 183
... PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) An error-insertion function is available in the DS21Q55 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence ...
Page 184
Register Name: ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 Name WNOE — Default 0 0 Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 ER2 ER1 ER0 ...
Page 185
Number-of-Errors Registers The number-of-error registers determine how many errors are generated 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update ...
Page 186
Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: NOEL1 Register Description: Number-of-Errors Left 1 Register Address: EEh Bit # 7 6 Name ...
Page 187
... In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q55 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS21Q55 can be configured for channel or frame interleave ...
Page 188
Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 Name — IBS1 Default 0 0 Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 DA1 DA0 ...
Page 189
... Figure 26-1. IBO Example RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER DS21Q55 #1 RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER DS21Q55 #2 189 of 237 8.192MHz SYSTEM CLOCK IN SYSTEM 8kHz FRAME SYNC IN PCM SIGNALING OUT PCM SIGNALING IN PCM DATA IN PCM DATA OUT ...
Page 190
... ESIBCR2) and four information registers (ESIB1, ESIB2, ESIB3, and ESIB4). For example, two DS21Q55s can be grouped into an ESIB group. A single read of the ESIB1 register of any member of the group yields the interrupt status of all eight ports of the two DS21Q55s. Therefore, the host can determine which device or devices are causing an interrupt without polling all eight devices ...
Page 191
Register Name: ESIBCR1 Register Description: Extended System Information Bus Control Register 1 Register Address: B0h Bit # 7 6 Name — — Default 0 0 Bit 0/Extended System Information Bus Enable (ESIEN disabled 1 = enabled Bits 1 ...
Page 192
Register Name: ESIBCR2 Register Description: Extended System Information Bus Control Register 2 Register Address: B1h Bit # 7 6 Name — ESI4SEL2 Default 0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what ...
Page 193
Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 Name DISn DISn Default 0 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to ...
Page 194
... PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include generation of port and backplane system clocks. The CCR2 register is used to enable (CCR2.0) and select (CCR2.1 and CCR2.2) the clock frequency of the BPCLK pin ...
Page 195
... FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN- PRI applications. The receive and transmit paths have independent enables. Channel formats supported include 56kbps and 64kbps. This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins ...
Page 196
Register Name: CCR3 Register Description: Common Control Register 3 Register Address: 72h Bit # 7 6 Name TMSS INTDIS CTTUI Default 0 0 Bit 0/Receive Gapped-Clock Enable (RGPCKEN RCHCLK functions normally 1 = enable gapped bit-clock output on ...
Page 197
Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 Name RLT3 RLT2 Default 0 0 Bit 0/Reserved, must be set to 0 for proper operation. Bit 1/ Reserved, must be set to 0 ...
Page 198
... The DS2Q155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Figure 30-1.). The DS21Q55 contains the following features as required by IEEE 1149.1 standard test access port (TAP) and boundary scan architecture. § Test Access Port § ...
Page 199
TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 30-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The ...
Page 200
Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. ...