PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet - Page 130

• Manufacturer Part Number: PEB 3086 F V1.4
• Description: IC ISDN ACCESS CTRLR TQFP64
• Manufacturer: Infineon Technologies
• Series: ISAC™r

Specifications of PEB 3086 F V1.4

• Function: Subscriber Access Controller
• Interface: HDLC, IOM-2, ISDN, Parallel, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: D-Channel Access Control and Priority Handler, Monitor Channel Handler, Non-Auto Mode, Transparent Mode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3086FV1.4XT; PEB3086FV14NP; PEB3086FV14XP; SP000007571; SP000007572

3.7.6
The IOM-2 interface can be switched off in the inactive state, reducing power
consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and
the data lines are ’1’.
The IOM-2 interface can be kept active while the S interface is deactivated by setting the
CFS bit to "0" (MODE1 register). This is the case after a hardware reset. If the IOM-2
interface should be switched off while the S interface is deactivated, the CFS bit should
be set to ’1’. In this case the internal oscillator is disabled when no signal (info 0) is
present on the S bus and the C/I command is ’1111’ = DIU. If the TE wants to activate
the line, it has first to activate the IOM-2 interface either by using the "Software Power
Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again.
The deactivation procedure is shown in
(Deactivate Indication Upstream) the layer 1 of the ISAC-SX responds by transmitting
DID (Deactivate Indication Downstream) during subsequent frames and stops the timing
signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth frame.
Figure 70
The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the
IOM_CR register), i.e. the C/I command TIM = "0000" is received by layer 1, or when a
non-zero level on the S-line interface is detected (if TR_CONF0.LDD=0). The clocks are
turned on after approximately 0.2 to 4 ms depending on the oscillator.
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
Data Sheet
IOM
FSC
DU
DCL
DD
Ò
-2
DR
Activation/Deactivation of IOM-2 Interface
DI
Deactivation of the IOM-2 Interface
DR
DI
DR
DI
DR
DI
DR
DI
130
DC
DI
Figure
B1
DC
DI
70. After detecting the code DIU
Description of Functional Blocks
D
B2
DC
DI
ITD09655_s.vsd
CIO
D CIO
DC
DI
IOM
Deactivated
Ò
-2
PEB 3086
2003-01-30
ISAC-SX