SC16C550BIA44,512 NXP Semiconductors, SC16C550BIA44,512 Datasheet - Page 22

• Manufacturer Part Number: SC16C550BIA44,512
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C550BIA44,512

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274387512; SC16C550BIA44; SC16C550BIA44

NXP Semiconductors
SC16C550B_5
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 12.
The SC16C550B provides four levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 13 “Interrupt source”
levels and the interrupt sources associated with each of these interrupt levels.
Table 13.
Table 14.
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
Bit
7:6
5:4
3:1
0
ISR[3]
0
0
1
0
0
RX trigger levels
Interrupt source
Interrupt Status Register bits description
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
FCR[6]
0
1
0
1
ISR[2]
1
1
1
0
0
Rev. 05 — 1 October 2008
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
not used
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
shows the data values (bits 3:0) for the four prioritized interrupt
RX FIFO trigger level (bytes)
1
4
8
14
ISR[1]
1
0
0
1
0
ISR[0]
0
0
0
0
0
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
SC16C550B
Table
© NXP B.V. 2008. All rights reserved.
13).
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