TDA7572 STMicroelectronics, TDA7572 Datasheet
TDA7572
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TDA7572 Summary of contents
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... IC. Digital Audio input is supported by an integrated one channel DAC. Sophisticated diagnostics and protection provide fault reporting via I power shutdown for safety related faults. TDA7572 is packaged in a HiQUAD-64 package. Package HiQUAD-64 Rev 1 TDA7572 Preliminary Data ...
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... Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 Input stage and gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/64 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Op. amp. cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TDA7572 ...
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... TDA7572 6.2 Gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 6.2.2 7 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 FET drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 ANTI-POP shunt driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 Step- Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1 Faults during operation 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 Under voltage lock out (UVLO 12.1 VSP-UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.2 V14 - UVLO ...
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... Contents 14.3 THD+N step- Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/64 TDA7572 ...
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... TDA7572 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin list by argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Pin list by pin Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Thermal data Table 6. Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12 ...
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... Figure 11. Threshold of current limiting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 12. Single supply evaluation board schematic Figure 13. Single supply evaluation PCB Figure 14. Split supply evaluation board schematic Figure 15. Split supply evaluation PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 16. THD+N step- Figure 17. HiQUAD-64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6/64 2 Cbus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TDA7572 ...
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... TDA7572 1 Detailed features ● Input Stage and Gain Compressor – Differential, high CMRR, analog input – Programmable input attenuation/gain to support up to four drive levels – Noiseless Gain compression with programmable attack and decay. – Compressor controlled by monitoring estimated THD – Soft mute / un-mute for pop control ● ...
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... I Cbus UVLO Thermal management Diff -to-S.E. Compressor Diagnostics and + Limiter clipdet Oscillators Channel 1 Controls and Diagnostics TDA7572 2 C bus, if one is present. This 2 C bus is present, while allowing full 2 C. LSD1SourceSensing PWM Channel 1 DAC LSD1GateDrive Pulse Inj . LSD1GateSensing Integrator HB1OutFilter HB1Out ...
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... TDA7572 3 Pins description Figure 2. Pins connection (top view) 1 Iset 2 TestC 3 LSD2SS 4 LSD2GD 5 LSD2GS 6 HB2OutFilt 7 HB2Out 8 HSD2GS 9 HSD2GD HSD2SS 10 VSP_POW2 11 12 VSP_POW1 13 HSD1SS 14 HSD1GD HSD1GS 15 HB1Out 16 17 HB1OutFilt 18 LSD1GS LSD1GD 19 LSD1SS Pins description SVR 51 VM2.5 50 VDIG 49 DGND 48 NTC 47 SCL/InLevel1 46 WS/Clip_L 45 SDA/SCR_ENB 44 PLL/InLevel10 ...
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... Lowside1 Gate sense Half bridge1 post-LC filter – for diagnostics Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense Highside1 Gate sense Highside1 Gate Drive Highside1 Source sense Positive supply voltage connection for gate drive circuitry TDA7572 2 C/diagnostic operation 2 C/diagnostic operation Section 8 2 ...
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... TDA7572 Table 2. Pin list by argument (continued) Pin # Pin name 39 MOD2 10 HSD2SS 9 HSD2GD 8 HSD2GS 7 HB2Out 6 HB2OutFilt 5 LSD2GS 4 LSD2GD 3 LSD2SS 27 VSM1 26 VSM2 58 VSM3 59 VSM4 43 ShuntDriver DC-DC 28 BSTVSense 22 BSTSource 21 BSTGate 23 CSense 24 V14Sense 25 V14 Oscillator 41 CLKIN/Out 42 DITH 40 OscOut Diagnostics / Bus 2 I CDATA/AttackSel CLK Description Modulator2 Inverting / Summing node ...
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... Highside2 Gate Drive Highside2 Source sense Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two Positive supply voltage connection for gate drive circuitry Highside1 Source sense Highside1 Gate Drive Highside1 Gate sense TDA7572 ...
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... TDA7572 Table 3. Pin list by pin (continued) Pin # Pin name 16 HB1Out 17 HB1OutFilt 18 LSD1GS 19 LSD1GD 20 LSD1SS 21 BSTGate 22 BSTSource 23 CSense 24 V14Sense 25 V14 26 VSM2 27 VSM1 28 BSTVSense 29 ISSENM 30 ISSENP 31 DAC2 32 DAC1 33 INM 34 INP 35 AOUT 36 InvIn 37 InvOut 38 MOD1 39 MOD2 40 OscOut 41 CLKIN/Out 42 DITH 43 ShuntDriver 44 PLL/InLevel0 45 SDA/SCR_ENB Clip_L 47 SCL/ InLevel1 ...
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... I C address set (I C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled data (I C mode) Compressor aggressiveness selection (non-bus mode Clock Output stage Current Limiting trip voltage setpoint TDA7572 2 C/diagnostic operation 2 C/diagnostic operation ...
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... TDA7572 4 Electrical specifications 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameters V Supply voltage SP V Peak supply voltage peak V Data pin voltage DATA T Junction temperature J T Storage temperature Stg P Power Dissipation DMAX 4.2 Thermal data Table 5. Thermal data Symbol R Thermal resistance junction to case Th j-case 4 ...
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... Vautomute VSetting-V SVR The IC is set in tristate if VSP-VSM is higher than this value Min. Typ. Max 25° 85° Min. Typ. 0.5 VVSVR* -15% +15% 7 =VVSVR VVSVR -15% +15% *12 =VVSVR VVSVR -15% +15% *13 =VVSVR VVSVR* -15% +15% 48 =VVSVR 60 63 TDA7572 Units V μ Max. Units 2 ...
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... TDA7572 Table 7. Under voltage lockout (continued) Symbol Parameters V14 – UVLO Auto-tristate supply V14- voltage V14 negative slope Auto-tristate supply V14+ voltage V14 positive slope Auto-tristate 14V voltage V14h hysteresis V14su Step-up tristate Auto-mute supply V14mute- voltage V14 negative slope Auto-mute supply ...
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... INLEVEL1=1, INLEVEL0=0 no compression ( (VInP-VinM) AOUT SVR INLEVEL1=1, INLEVEL0=1, no compression With respect to SVR, 10K loading to a buffered version of SVR With respect to SVR, 10K loading to a buffered version of SVR Vin=1Vrms, f=20-20KHz, INLEVEL1=0, INLEVEL0=0, no compression TDA7572 Min. Typ. Max. Units -30% 20 +30% -30% 12 +30% -30% 22 +30% -30% 12 +30% KΩ ...
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... TDA7572 Table 8. Input stage Symbol Parameters Output slew rate AOUT clip detector f Frequency response -3dB Common Mode Rejection CMRR Ratio CG Common gain CG Common gain CG Common gain CG Common gain Power Supply Rejection, PSRR Vsp supply V Output offset offset Eno Noise Gain compressor ...
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... Mute pin voltage = Dgnd Vin=1Vrms Mute Pin Voltage(57) = 1.5V Mute Pin Voltage(57) = 1.5V Maximum voltage where we must be in complete mute IC in mute mode, FastMute=1 Iout unmute, Iout=0 FASTMUTE=1 Vmutepin=1.5Volts TDA7572 Min. Typ. Max. Units 0.5+ 0.5-0.25 0.5 0.25 0.44- 0.44+ 0.44 ...
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... TDA7572 4.3.4 Oscillator Table 9. Oscillator Symbol Parameters Internal oscillator F Switching frequency PWM_NOM CLK Duty cycle DC V Maximum voltage level CLK_High V Minimum voltage level CLK_Low V Peak-peak voltage CLK-P-P Dither cap charge current Dither pin voltage= 2.5V Dither cap discharge current Peak-peak dither voltage ...
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... I = 20mA source After a commutation After a commutation V =V t>5uS HSG t>5uS LSG SM Engagement of the current limiting VlimitTreshold=1V w.r.t. VM2p5 Start of cycle by cycle current limiting TDA7572 Min. Typ. Max. Units -2.5 +2.5 mV 500 nA 1.1 µs Min. Typ. Max. Units 1.75 V 0.080 ...
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... TDA7572 Table 11. Gate drive and output stage control (continued) Symbol Parameters NFET gate voltage that will NV GS_ON block PFET enhancement NFET gate voltage that will NV GS_OFF allow PFET enhancement 4.3.7 Diagnostics Table 12. Diagnostics Symbol Parameters Turn-on diagnostics/ Power up diagnostics I Test current for short/open ...
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... V at max current C_SENSE Csense Ilimit trip point Trip Soft-start step period T not yet tested ( confirmed) Soft start steps 24/64 Test conditions -15% Vdig*0.0 -25% Test conditions V V Vsense = reference DC=0% TDA7572 Min. Typ. Max. Units V *.36 +15% V DIG Vdig* 046 +25% ms 200 700 µ ...
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... TDA7572 Table 13. Voltage booster Symbol Parameters V BST gate high voltage OH_BST V BST gate low voltage OL_BST 4.4.1 Digital to analog converter Table 14. Digital to analog converter Symbol Parameters Dynamic range at -60dBFS Noise floor THD+N at maximum useful input level Silent Mute Differential output voltage ...
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... Shunt drive current V sdh activation hysteresis 26/64 Test conditions V <375mV SCL/CLIP_L Test conditions Guaranteed by design PSRR = 20*log10(Vsp/= F < 10KHz V ripple=1Vrms SP Guaranteed by design Guaranteed by design Guaranteed by design Test conditions TDA7572 Min. Typ. Max. Units -15 15 µ 1 Min. Typ. Max. Units ...
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... TDA7572 4.4.5 Application information These are required parameters of the overall operation of the Cortina IC in its application circuit and will form the overall functional testing for Cortina Table 18. Analog operating characteristics Symbol Parameters THD+Noise Output noise Output offset Output offset 1. Note: the measure is affected by the testing board noise. ...
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... I C and mode control The Mode1 and Mode0 pins are used to enable TDA7572. These perform the function of bringing the IC out of standby (typically handled by a single standby pin on most audio IC's) as well as determining if the I occurs. The Auto-mute Voltage pin is used to provide an under-voltage-lockout for the IC. Using a ...
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... TDA7572 The protocol used for the bus is the following and comprises: ● a start condition (S) ● a chip address byte (the LSB bit determines read / write transmission) ● a subaddress byte ● a sequence of data (N-bytes + acknowledge) ● a stop condition (P) Table 20. Addresses Chip address MSB ...
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... Example of read instruction with increment and previous addressing by write instruction and restart bit (Sr) Device Register R/W Address Address S 0011000 0 A ADDR In the following tables are reported the meaning of each I 30/64 Device R/W DATA 1 Address A Sr 0011000 1 A MS1 A LS1 A MS2 A LS2 A MSn A LSn NA P TDA7572 DATA 2 DATA bus present in the device. ...
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... TDA7572 5.1 Input control register Subaddress: XXI00001. Table 22. Input control register MSB R/W R/W R AttackSel AttackSel (pin)=1 → [11] (pin)=1 → [11] AttackSel AttackSel (pin)=0 → [10] (pin)=0 → [10 R/W R/W R/W R CompEnable Read (pin)=1 → [01] from PLL/Gain CompEnable (pin)=0 → [00 and mode control ...
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... R/W1TC Power- default GNDshort 0 Short to ground 1 detected V short Short to a “Vcc” detected Open/offset Open load detected during LOADshort Short across the load detected DiagnENB Diagnostic disabled or finished To run the Diagnostic/diagnostic in progress UVLO flag UVLO event NOT USED NOT USED TDA7572 ...
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... TDA7572 5.3 Faults 2 register Subaddress: XXI 00011. Table 24. Faults 2 register MSB R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC and mode control LSB Function R/W1TC Power- default Clip 0 Clipping of modulator 1 and/or preamplifier Offset 0 1 Offset detected IsenTrip Power supply current threshold trespass IoutTrip Output stage current ...
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... R 34/ R/W R/W R SDA/SCR_ENB TDA7572 LSB Function R/W Power-up default enabled Power-up Default disabled Mute speed 0 Slow Mute 1 Fast Mute OffsetENB 0 Enable the offset 1 detection PassFET Control ENB Enable the SCR intervention BOOST Enable the step-up L/R Read left channel from 2 I ...
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... TDA7572 5.5 Modulator register Subaddress: XXI 00101. Table 26. Modulator register MSB R/W R/W R/W R R/W R/W R SCL/InLevel1 0 pin and mode control LSB Function D 0 R/W 2 Power-up default disabled 2 Power-up default enabled SHUNT 0 Turn-on shunt 1 NOT USED INLEVEL1 High level couple DAC synchronization ...
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... R/W R/W R TDA7572 Function Power-up default Or ZC (nIN xnor pIN) or (nOUT xnor pOUT) are put on the clipping output Ramp Generate a ramp on the compressor gain TestDriving Turn off limitation of driving current for the external MOS Fast All time constant used in the logic ...
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... TDA7572 6 Input stage and gain compressor 6.1 Input stage The input stage accepts differential analog audio and provides a single ended output that is referenced to SVR, a slowly changing reference signal that is close to V present on the pin 6 (SVR). Four input stage gains are selectable, chosen such that input signal levels of either 2V output swing of this stage ...
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... Sets the maximum release rate of the gain compressor Release [1: 38/64 Pseudo THD,% / T2/T1 ratio Gain compressor disabled 0.02 3.0 0.02 3.0 5.0 0.02 3.0 5.0 15.0 Clock counts TDA7572 2 C bus registers and coefficients for Number of gain steps Nominal time at 400KHz clock 20.48ms 40.96ms 81.92ms 163.4ms ...
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... TDA7572 ATTACK[1:0]: Sets the maximum Attack rate of the gain compressor according to the table below: Table 30. Sets the maximum attack rate of the gain compressor Attack [1: Setting in NOI CBUS mode CDATA/AttackSel - pin 51 -> Attack/release rate selection ADDR1/CompEnable - pin 54 -> Gain compression effort selection Table 31 ...
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... TRISTATE the mute pin is fast-discharged by the fast-mute internal circuitry. When the modulator is take back out of TRISTATE the preamplifier is put in play back by a fast un-mute transient. 40/ bus command 100µA Mute_L 500Ohm 200µA Mute and not(MuteSpeed) TDA7572 Mute and MuteSpeed AC00016 ...
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... TDA7572 7 Modulator The modulator PWM is the main function of device. Two modulators are provided which are operated independently but configured for bridged mono operations. They are synchronized by virtue of the common clock that drives them and operate as a three-state modulator (phase shifting PWM modulation type) when the audio is inverted going to one modulator. ...
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... F /2 NOM F NOM F *2 NOM F NOM limits. A separate regulator 10V below each FET with a dedicated sense line GS |. This allows discrete components to be used to adjust gate charging signal is blanked such that sensing is only active DS TDA7572 Nominal frequency 55KHz 110KHz 220KHz 110KHz , is used SP ...
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... TDA7572 consists in a clipping of current when the first threshold for V by sink or source current to the virtual ground of modulator integrator. The cycle-by-cycle limitation is a strong limitation. If the second V about 2µs the half bridge is tri-stated. If this condition persists for more then four PWM periods the modulator is definitely tri-stated ...
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... Coefficients Half-Band filter then we have only 15 Coefficients: -11,11,-16,22,-30,40,-53,69,-91,122,-168,247,-426,1300,2047,1300,…. 44/64 CF R=2.5k RF RF=4.7k DAC2 port available too. Increasing word rate from Fs to 2Fs. Remez filter, half band 57, 12 50db attenuation out of 0.55Fs coefficients (see following) TDA7572 R=20k INP CF INM SVR/DGND AC00019 ...
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... TDA7572 In case of Fratio = "11" the configuration is still for full band. The input sample rate for this case is 192kHz (Fs) and the first x4 interpolator has to be implemented off-line in the DSP. For the first x2 interpolator could be used the precedent, for the second one should be used ...
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... Csense exceeding a voltage threshold and are handled by forcing a restart of the soft start sequence when over-current is declared. Following are reported the threshold of current limiting. 46/64 14V VSP V14Sense CSense Step-Up Regulator BSTGate BSTSource BSTVSense VSM VSM TDA7572 +14V Coil R2 R1 AC00022 ...
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... TDA7572 Figure 11. Threshold of current limiting diagram Vlimhmax, Vlimlmax 440mV AC00023 2 The I C bus register that is set for default to "habilitation" enables the step up. In case of 14V operation or split supply the step-up and no i2c bus mode the step-up is disabled by connects the BSTVSense pin to a reference of at least five volts over VSM. ...
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... used to assert when clipping occurs. In this case the Address0 of I automatically set to zero, which implies that only two TDA7572 can be addressed. In any Mode case a clipping output is present. The detailed procedure implemented to manage these faults follows: 10 ...
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... TDA7572 10.1.2 Die temperature 2 ● I Cbus: The Twarn bit in register Faults2 bus register is set when the first threshold is exceeded. If the second threshold is exceeded the SCR is enabled (only if the PassFETctrl bit is set to one) which allows the external power switch to latch off, and can only be restarted by removing and reapplying power ...
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... Clip the output current by modulator injection - Latch the IoutTrip bit - The SCR is activated if enabled - Latch the IoutTrip bit - Assert the Fault pin - The SCR is activated if enabled 2 C bus) the Output over-current warning information is not reported on TDA7572 Threshold The SCR is activated if enabled Cycle-to-cycle Current limiting is activated. ...
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... TDA7572 Events that put in tri-state the Modulator: – Diagnostic on – Offset detection – Output over-current second threshold trespassed Events that enable the Fault Pin without I – Diagnostic Fault – Junction thermal warning – External thermal warning – Supply current over-threshold – ...
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... These are instead the thresholds to take into account for the short and open transducers with some example with a predefined current Voltage threshold Itest=14mA Itest=140mA 52/ Normal load - 0.4Ω 1.43Ω - 0.04Ω 0.14Ω TDA7572 71Ω 143Ω - 7.1Ω 14.3Ω - ...
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... TDA7572 11 Oscillator A common clock is needed to run all switching blocks at one frequency to avoid beating. The internally generated clock is used for the PWM modulators and to run the dc-dc converter. To blur the EMI spectrum, sub-audible frequency dither incorporated. ● When the DITH-sel pin is logic gnd then the internal oscillator operates without dither. ...
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... The V14-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity. 54/64 TDA7572 ...
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... TDA7572 12.3 SVR - UVLO This block monitors the SVR-VSM drop voltage and eventually moves the modulator in tristate. The SVR-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity ...
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... V U CBUS MODE set to '1' when the digital supply pin VDIG (50) reaches its 2 C bus is written '1' on the D4 bit of modulator register. CDIAGNOSTIC set to '1' when the digital supply pin VDIG (50) reaches its ? UC TDA7572 ...
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... TDA7572 14 Applications 14.1 Single supply Figure 12. Single supply evaluation board schematic. Applications 57/64 ...
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... Applications Figure 13. Single supply evaluation PCB 58/64 Top layer and component layout Bottom layer TDA7572 AC00111 AC00112 ...
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... TDA7572 14.2 Split supply Figure 14. Split supply evaluation board schematic. Applications 59/64 ...
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... Applications Figure 15. Split supply evaluation PCB 60/64 Top layer and component layout Bottom layer TDA7572 AC00114 AC00115 ...
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... TDA7572 14.3 THD+N step-up on The graph below report the THD+N vs. Pout of a TDA7572 board with step-up on and 50Hz input sine wave. Condition and step to made the board working are: 1. connect a voltage supplier to the connector J1: Positive terminal (max 14V) connected to L14V, ground terminal connected to -Vs. ...
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... ⊕ slug (bottom side (slug lenght OUTLINE AND MECHANICAL DATA HiQUAD- BOTTOM VIEW Gauge Plane C 0. SEATING PLANE COPLANARITY A1 POQU64ME TDA7572 ...
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... TDA7572 16 Revision history Table 34. Document revision history Date 3-Sep-2007 Revision 1 Initial release. Revision history Changes 63/64 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 64/64 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com TDA7572 ...