TDA9116 STMicroelectronics, TDA9116 Datasheet
TDA9116
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TDA9116 Summary of contents
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... Bus-controlled output voltage Synchronization on hor. frequency with phase selection Selectable polarity of drive signal DESCRIPTION The TDA9116 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. ...
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GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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10.8.2 -Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... TDA9116 1 - GLOSSARY AC Alternate Current ACK ACKnowledge bit of I AGC Automatic Gain Control COMP COMParator CRT Cathode Ray Tube DC Direct Current EHT Extra High Voltage EW East-West H/W HardWare HOT Horizontal Output Transistor Inter-Integrated Circuit IIC Inter-Integrated Circuit MCU Micro-Controller Unit NAND Negated AND (logic operation) ...
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... HLckVBk 3 30 HOscF 29 4 HPLL2C HGND HPLL1F 24 9 HPosF 23 10 HMoiré HFly 21 12 RefOut 13 20 BComp 14 19 BRegIn 18 15 BISense 16 17 TDA9116 VDyCor SDA SCL Vcc BOut GND HOut XRay EWOut VOut VCap VGND VAGCCap VOscF VEHTIn HEHTIn 5/47 ...
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... Vertical position S-correction Vertical moiré C-correction VDyCor VOut VEHTIn VCap HPLL2C 5 H-drive HOut 26 buffer Safety XRay 25 processor BOut 28 B+ PLL2 BISense 16 DC/DC converter BRegIn 15 controller B+ ref. BComp 14 HMoiré generator H size Pin cushion EWOut 24 Keystone Top corners Bottom corners TDA9116 17 HEHTIn ...
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... XRay X-Ray protection input 26 HOut Horizontal drive Output 27 GND Main GrouND 28 BOut B+ DC/DC converter controller Output 29 Vcc Supply voltage 2 30 SCL I C bus Serial CLock Input 2 31 SDA I C bus Serial DAta input/output 32 VDyCor Vertical Dynamic Correction output Function TDA9116 7/47 ...
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... TDA9116 5 - QUICK REFERENCE DATA General Package Supply voltage Supply current Application category Means of control/Maximum clock frequency EW drive DC/DC converter controller Adjustable DC level output Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive/Negative polarity of horizontal sync signal/Automatic adaptation Duty cycle range of the drive signal ...
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... ESD susceptibility V ESD (human body model: discharge of 100pF through 1. Storage temperature stg T Junction temperature j Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. Parameter TDA9116 Value Unit Min Max -0.4 13 -0.4 5 ...
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... TDA9116 7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS The medium (middle) value adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". The minimum value is the one with all bits at 0, maximum value is the one with all at "1". ...
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... At top of H flyback pulse No PLL2 phase modula- (6) tion (5) (5) Null asym. correction (7) Null asym. correction (8) Output driven LOW HDUTY (Sad00): x1111111b x0000000b Soft-start/Soft-stop value HPOS (Sad01): 1111111xb 0000000xb TDA9116 Value Min. Typ. Max. 1.5 390 150 =820pF 27 28.5 29 122 -150 19.6 1.4 6 ...
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... TDA9116 Symbol Parameter Contribution of pin cushion asymmetry t /T correction to phase of H-drive vs. static PCAC H phase (via PLL2), measured in corners Contribution of parallelogram correction phase of H-drive vs. static phase (via ParalC H PLL2), measured in corners Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency ...
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... VEHT change. . Value Min. Typ. 80 100 50 (12) 0.5 (13) (15 (14) (15 200 <f <f (max) VO VOCapt 3.2 3.5 3.65 3.8 2.25 3.0 3 <V 2.5 VEHT RefO " is duration of this ramp, see VR TDA9116 Units Max 185 ppm RefO %/V %/V 13/47 ...
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... TDA9116 7 DRIVE SECTION V = 12V 25°C CC amb Symbol V Output voltage on EWOut pin EW Current sourced by EWOut out- I EWOut put Control voltage range on HEH- V HEHT TIn pin DC component of the EW-drive V EW-DC signal on EWOut pin V Breathing compensation – ---------------------------- - V V EW-DC HEHT Temperature drift of DC compo- ...
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... VR 2 VDyCorPol I C Bus bit. Refer to section I Value Min. Typ 1.75 HEHT RefO =1 =1 > HOThrfr Value Min. Typ. -1.5 =10k 4 0 0.5 1 0.6 1.6 0.52 1. Bus control register map. TDA9116 Units Max. %/V %/ Units Max 15/47 ...
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... TDA9116 7.8 - DC/DC CONTROLLER SECTION V = 12V 25°C CC amb Symbol Parameter Ext. resistance applied between R B+FB output and BComp Open loop gain of error amplifier A OLG on input BRegIn Unity gain bandwidth of error am- f UGBW plifier on BRegIn Bias current delivered by regula tion input BRegIn ...
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... HMoiMode=0 (internal) Rext=10k VOLCTRL (Sad04): x0000000b x1111111b HMoiMode=1 (external) Rext=10k VMOIRE (Sad0Bh): x0000000b x1111111b XRay (40) input CC CC (18)(42) Normal operation HPOS (Sad01) 0000000xb 1111111xb TDA9116 Value Min. Typ. Max. 100 H.lock 0.1 Yes Yes 1 0.04 0.1 2.1 0.1 5 0.1 ...
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... TDA9116 Note 39: Current sunk by the pin if the external voltage is higher than one the circuit tries to force. Note 40: The threshold is equal to actual V Note 41: In the regions of V where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on CC HOut, VOut and BOut pins, resp., are inhibited, the I flag is reset ...
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... VOut Byte Waveform V x0000000 amp(min) V mid(VOut) V x1111111 amp(max) V mid(VOut) x0000000 V mid(VOut) x1000000 V mid(VOut) V mid(VOut) x1111111 x0000000: V VOamp Null V VOS-cor V x1111111: VOamp Max. 0 ¼T ¾ VOamp x0000000 V VOC-cor 0 ½T VR x1000000 : V VOamp Null V VOamp V x1111111 VOC-cor 0 ½T VR TDA9116 Effect on Screen 3.5V 3.5V 3. 19/47 ...
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... TDA9116 Function Sad Pin Vertical moiré 0B VOut amplitude Horizontal size 10h EWOut Keystone 0D EWOut correction Pin cushion 0C EWOut correction Top corner 0E EWOut correction Bottom corner 0F EWOut correction 20/47 Byte Waveform V amp x0000000: Null (n-1 amp x1111111: Max. (n-1 0000000x EW-DC(min) 0 ½ ...
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... Waveform static phase t ParalC(min) x0000000 0 ½ ParalC(max) static phase x1111111 0 ½ PCAC(max) x0000000 0 ½ PCAC(max) x1111111 0 ½ VD-V(max) 01111111 0 ½ VD-V(max) x0000000 0 ½ VD-V(max) 11111111 0 ½T VR TDA9116 Effect on Screen static H-phase static H-phase VDyCorPol=0 V VD- VD-DC Application dependent VDyCorPol=1 V VD- 21/47 ...
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... TDA9116 BUS CONTROL REGISTER MAP The device slave address write mode and 8D in read mode. Bold weight denotes default value at Power-On- Reset Bus data in the adjustment register is buffered Sad D7 D6 WRITE MODE (SLAVE ADDRESS = 8C) HDutySyncV 00 1: Synchro Asynchro HMoiré Separated ...
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... HOut pin, selected by BOHEdge bit Sad08/D7 - EWTrHFr Tracking of all corrections contained in wave- form on pin EWOut with Horizontal Frequency 0: Not active 1: Active Sad15/D7 - VDyCorPol Polarity of Vertical Dynamic Correction wave- form (parabola) 0: Concave (minimum in the middle of the pa- rabola) 1: Convex (maximum in the middle of the pa- rabola) TDA9116 ...
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... TDA9116 Sad16/D0 - HLockEn Enable of output of Horizontal PLL1 Lock/unlock status signal on pin HLckVBk 0: Disabled, vertical blanking only on the pin HLckVBk 1: Enabled Sad16/D1 - PLL1InhEn Enable of Inhibition of horizontal PLL1 during extracted vertical synchronization pulse 0: Disabled, PLL1 is never inhibited 1: Enabled Sad16/D2 - PLL1Pump Horizontal PLL1 charge Pump current ...
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... Locked (amplitude stabilized) 1: Not locked (amplitude non-stabilized) SadXX/D7 - HLock Status of Locking of Horizontal PLL1 0: Locked 1: Not locked Bus bit). This taken into account by application S way SDetReset bit and validation of information provided in the flag after read- TDA9116 2 C Bus bit XRayReset or by power- 25/47 ...
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... TDA9116 10 - OPERATING DESCRIPTION 10.1 - SUPPLY AND CONTROL 10.1.1 - Power supply and voltage references The device is designed for a typical value of power supply voltage order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value monitored. See Figure 1 and electrical CC specifications. At switch-on, the device enters a “ ...
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... VCO ramp by a comparator with threshold adjustable through HPOS I trol. The coincidence is identified and flagged by lock detection circuit on pin HLckVBk as well as by HLock bus bit, the reset action 2 C bus transfer bus bits switching the 2 C bus flag. TDA9116 2 C bus con- 27/47 ...
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... TDA9116 The charge pump provides positive and negative currents charging the external loop filter on HPosF pin. The loop is independent of the trailing edge of sync. signal and only locks to its leading edge. By design, the PLL1 does not suffer from any dead band even while locked. The speed of the PLL1 depends on the current value provided by the charge pump ...
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... As all the compo- nents of the resulting correction waveform (linear for parallelogram correction and parabola of 2nd order for Pin cushion asymmetry correction) are HOscF Flip-Flop - + VCO discharge control V HOThrHi V HOThrLo TDA9116 is com- S(0) 29/47 ...
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... TDA9116 generated from the output vertical deflection drive waveform, they both track with real vertical ampli- tude and position (including breathing compensa- tion), thus being fixed on the screen. Refer to I BUS CONTROL REGISTER MAP on page 22 for 2 details bus controls. Figure 7. Horizontal timing diagram ...
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... The higher its parallel resistance R L(VAGCCap) When the synchronization pulse is not present, the charging current is fixed consequence, the free-running frequency f value of the capacitor on pin VCap. It can be roughly calculated using the following formula TDA9116 2 C bus bit. This bit kept minimum value 2 HPOS (I C) ...
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... TDA9116 150nF . 100Hz f = VO(0) C (VCap) The frequency range in which the AGC loop can regulate the amplitude also depends on this ca- pacitor. The C- and S-corrections of shape serve to com- pensate for the vertical deflection system non-line- arity. They are controlled via CCOR and SCOR ...
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... It can be switched off by EWTrHFr I by default). The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is directly routed to EWOut output, with no internal resistor to ground biased externally. TDA9116 2 C bus 2 C bus controls through bus bit (off ...
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... TDA9116 Figure 12. Geometric corrections’ schematic diagram Controls: one-quadrant two-quadrant V mid(VOut) 2 VOut 23 Top parabola generator Vertical ramp Bottom parabola generator 34/47 VDC-AMP 2 PCC TCC ( BCC (I C) KEYST VDyCorPol ( Tracking HEHTIn/HSize 2 Tracking (I C) with Hor Frequency 2 PCAC ( horizontal 24 dyn. phase control 2 PARAL (I ...
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... DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry (e.g. current through external power component). The polarity of the output can be controlled by BOutPol I bit. A NPN transistor open-collector is routed out to the BOut pin. TDA9116 V (max EW-DC 2 ...
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... TDA9116 During the operation, a sawtooth found on pin BISense, generated externally by the applica- 2 tion. According to BOutPh I C bus bit, the R-S flip- flop is set either at H-drive signal edge (rising or falling, depending on BOHEdge I certain delay ( after middle of H-fly- BTrigDel H back. The output is set On at the end of a short pulse generated by the monostable trigger ...
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... X-ray condition detec- tion at short parasitic spikes. The XRayAlarm I bus flag is set inform the MCU. This protection is latched; it may be reset either drop bus bit XRayReset (see chap ter I C BUS CONTROL REGISTER MAP on page 22). TDA9116 threshold 37/47 ...
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... TDA9116 Figure 15. Safety functions - block diagram HBOutEn supervision V CC CCEn + V CCDis _ 29 Vcc XRayReset XRay H-VCO ThrXRay discharge HFly control ThrHFly VOutEn BlankMode HlockEn H-lock detector R V-sawtooth discharge S V-sync 38/ Out L1=No blank/blank level L2=H-lock/unlock level bit/flag HPosF 10 (timing) SOFT START & STOP ...
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... CCDis tive or if the V-drive signal is disabled by VOutEn bus bit +L2 (H) (L) +L2 (L) No Yes Yes 2 C bus bit, when 2 C bus bit, is also thresholds), if the X-ray protection is ac blank/blank level L2 - H-lock/unlock level L1 +L2 (H) (H) +L2 (L) (H) No Yes No No TDA9116 V CCEn 39/47 ...
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... TDA9116 Figure 17. Ground layout recommendations 40/ TDA9116 General Ground ...
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... INTERNAL SCHEMATICS Figure 18. 5V Pins 1-2 200 H/HVSyn VSyn Figure 19. 12V 13 HLckVBk l 3 Figure 20. 12V Pin 13 HOSCF Pin 4 Figure 21. HPLL2C Figure 22. RefOut 6 C0 Figure 23 RefOut 12V 13 5 12V RefOut 13 12V RefOut 13 TDA9116 41/47 ...
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... TDA9116 Figure 24. HPLL1F 9 Figure 25. RefOut 12V HPosF 10 Figure 26. 12V 5V HMoiré 11 42/47 Figure 27. HFly 12 Figure 28. BComp 14 Figure 29. 5V BRegIn 12V 12V 15 ...
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... Figure 30. 12V BISense 16 Figure 31. 12V 18 VEHTIn 17 HEHTIn Figure 32. 12V Pin 13 VOSCF 19 Figure 33. 12V VAGCCap 20 Figure 34. 12V 22 VCap Figure 35. 12V VOut 23 TDA9116 43/47 ...
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... TDA9116 Figure 36. 12V 24 EWOut 32 VDyCor Figure 37. 12V XRay 25 Figure 38. 12V 26 HOut 28 BOut 44/47 Figure 39. 30 SCL 31SDA ...
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... TDA9116 E E1 Stand-off eA eB Inches Min. Typ. 0.140 0.148 0.020 0.120 0.140 0.014 0.018 0.030 0.040 0.008 0.010 1.080 1.100 ...
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... TDA9116 PRODUCT PREVIEW September 2000 Document created from last version of TDA9113 with changes emphasized in red. In internal schematics, Pin 11 copied from TDA9115. November 23, 2000 correction in pages 11, 14, 17, 20: HPOS and HSIZE were described on 8 bits instead of 7. page 34:the unused current source has been deleted page 36, figure 14: text relative to int ...
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