M58LR128GB85ZB5 STMicroelectronics, M58LR128GB85ZB5 Datasheet
M58LR128GB85ZB5
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M58LR128GB85ZB5 Summary of contents
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Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) FEATURES SUMMARY SUPPLY VOLTAGE – 1.7V to 2.0V for program, erase and DD read – 1.7V to 2.0V for I/O Buffers DDQ – for fast ...
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M58LR128GT, M58LR128GB TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58LR128GT, M58LR128GB READ MODES ...
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Table 27. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M58LR128GT, M58LR128GB Table 50. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SUMMARY DESCRIPTION The M58LR128GT 128 Mbit (8 Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-sys- tem on a Word-by-Word basis using a 1.7V to 2.0V V supply for the circuitry ...
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M58LR128GT, M58LR128GB Figure 2. Logic Diagram DDQ A0-A22 W E M58LR128GT G M58LR128GB SSQ 8/84 Table 1. Signal Names A0-A22 DQ0-DQ15 DQ0-DQ15 W RP ...
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Figure 3. VFBGA56 Package Connections (Top view through package A11 B A12 C A13 D A15 E V DDQ DQ15 DQ14 G DQ7 V SSQ Table 2. Bank Architecture Number Parameter Bank Bank 1 Bank ...
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M58LR128GT, M58LR128GB Figure 4. Memory Map M58LR128GT - Top Boot Block Address lines A22-A0 000000h 64 KWord 00FFFFh Bank 15 070000h 64 KWord 07FFFFh 600000h 64 KWord 60FFFFh Bank 3 670000h 64 KWord 67FFFFh 680000h 64 KWord 68FFFFh Bank 2 ...
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SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A22). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. ...
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M58LR128GT, M58LR128GB V Ground. V ground is the reference for the SS SS core supply. It must be connected to the system ground. V Ground. V ground is the reference for SSQ SSQ the input/output circuitry driven by V must ...
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BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Ad- dress Latch, Output Disable, Standby and Reset. See Table 3., Bus Operations, for a summary. Typically glitches of less than 5ns ...
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M58LR128GT, M58LR128GB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the ...
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Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Lock Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue ...
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M58LR128GT, M58LR128GB teed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. Typical Erase times are 17., Program/Erase ...
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Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. See APPENDIX C., Figure 21., Buffer Program Flowchart ...
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M58LR128GT, M58LR128GB Enhanced Factory Program operation and re- turned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more ...
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The segments are programmed one Word at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two Bus Write cycles are required to issue the Protection Register ...
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M58LR128GT, M58LR128GB The first bus cycle sets up the Block Lock- Down command. The second Bus Write cycle latches the block address and locks-down the block. The lock status can be monitored for each block using the Read Electronic Signature ...
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Table 6. Factory Program Command Command Phase Setup 2 Buffer Enhanced Program/ 32 Factory (3)) Verify Program Exit 1 Note Word Address in targeted bank, BKA= Bank Address Program Data Block Address, X ...
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M58LR128GT, M58LR128GB Figure 5. Protection Register Memory Map Protection Register Lock 22/84 PROTECTION REGISTERS 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah 89h 88h 88h ...
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Table 8. Protection Register Locks Lock Number Address Lock 1 80h Lock 2 89h Bits preprogrammed to protect Unique Device Number, address 81h to Bit 0 84h in PR0 Bit 1 protects 64bits of OTP segment, address 85h to 88h ...
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M58LR128GT, M58LR128GB STATUS REGISTER The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for ...
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Once set High, the V Status bit must be set Low Clear Status Register command or a hard- ware reset before a new program or erase com- mand is issued, otherwise the new command will appear to ...
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M58LR128GT, M58LR128GB Table 9. Status Register Bits Bit Name SR7 P/E.C. Status SR6 Erase Suspend Status SR5 Erase Status SR4 Program Status SR3 V Status PP SR2 Program Suspend Status Status SR1 Block Protection Status Bank Write Status SR0 Multiple ...
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CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface using ...
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M58LR128GT, M58LR128GB chronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge ...
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Table 11. Configuration Register Bit Description CR15 Read Select CR14 Reserved CR13-CR11 X-Latency CR10 Wait Polarity Data Output CR9 Configuration CR8 Wait Configuration CR7 Burst Type CR6 Valid Clock Edge CR5-CR4 Reserved CR3 Wrap Burst CR2-CR0 Burst Length Note: 1. ...
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M58LR128GT, M58LR128GB Table 12. Burst Type Definition Start Add. 4 Words 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1-2 ... 7 7-4-5-6 ... 12 12-13-14-15 12-13-14-15-8-9-10-11 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 13 13-14-15-12 13-14-15-8-9-10-11-12 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 14 14-15-12-13 14-15-8-9-10-11-12-13 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15 15-12-13-14 15-8-9-10-11-12-13-14 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 0 ...
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Figure 6. X-Latency and Data Output Configuration Example 1st cycle (1) A22-A0 VALID ADDRESS DQ15-DQ0 Note: 1. The settings shown are X-latency = 4, Data Output held for one clock cycle. X-latency 2nd cycle 3rd cycle 4th ...
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M58LR128GT, M58LR128GB Figure 7. Wait Configuration Example A22-A0 VALID ADDRESS DQ15-DQ0 WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 ...
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READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchro- nous; if the data ...
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M58LR128GT, M58LR128GB Synchronous Burst Read Suspend. A chronous Burst Read operation can be suspend- ed, freeing the data bus for other higher priority devices. It can be suspended during the initial ac- cess latency time (before data is output) in ...
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DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE The Multiple Bank Architecture M58LR128GT/B gives greater flexibility for soft- ware developers to split the code and data spaces within the memory array. The Dual Operations fea- ture simplifies the software management of the ...
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M58LR128GT, M58LR128GB Table 15. Dual Operation Limitations Current Status Programming / Erasing Parameter Blocks Located in Parameter Programming / Bank Erasing Main Not Located in Blocks Parameter Bank Programming OTP 36/84 Commands allowed Read CFI / OTP / Read Parameter ...
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BLOCK LOCKING The M58LR128GT/B features an instant, individu- al block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software only ...
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M58LR128GT, M58LR128GB If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase Table 16. Lock Status Current (1) Protection Status (WP, DQ1, DQ0) ...
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PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in ble 17. Exact erase times may change depending on the memory array condition. The best case ...
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... Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn- assembly), the ST ECOPACK ® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 40/84 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter PPH ...
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DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
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M58LR128GT, M58LR128GB Table 21. DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=5MHz) I DD1 Supply Current Synchronous Read (f=54MHz) Supply Current I DD2 (Reset) I Supply Current ...
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Table 22. DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 Program Voltage Factory PPH ...
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M58LR128GT, M58LR128GB Figure 10. Asynchronous Random Access Read AC Waveforms 44/84 ...
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Figure 11. Asynchronous Page Read AC Waveforms M58LR128GT, M58LR128GB 45/84 ...
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M58LR128GT, M58LR128GB Table 23. Asynchronous Read AC Characteristics Symbol Alt t t AVAV AVQV ACC t t AVQV1 PAGE ( AXQX t ELTV ( ELQV ( ELQX t ...
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Figure 12. Synchronous Burst Read AC Waveforms M58LR128GT, M58LR128GB 47/84 ...
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M58LR128GT, M58LR128GB Figure 13. Single Synchronous Read AC Waveforms A0-A23 VALID ADDRESS L (2) K tELKH E G Hi-Z DQ0-DQ15 Hi-Z (1,2) WAIT Note: 1. The WAIT signal is configured to be active during wait state. WAIT signal is active ...
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Figure 14. Synchronous Burst Read Suspend AC Waveforms M58LR128GT, M58LR128GB 49/84 ...
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M58LR128GT, M58LR128GB Figure 15. Clock input AC Waveform tKHKL Table 24. Synchronous Read AC Characteristics Symbol Alt t t AVKH AVCLKH t t ELKH ELCLKH t ELTV t EHEL t EHTZ t t KHAX CLKHAX t KHQV t CLKHQV t ...
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Figure 16. Write AC Waveforms, Write Enable Controlled M58LR128GT, M58LR128GB 51/84 ...
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M58LR128GT, M58LR128GB Table 25. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH (3) Address Valid to Write Enable High t AVWH t ...
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Figure 17. Write AC Waveforms, Chip Enable Controlled M58LR128GT, M58LR128GB 53/84 ...
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M58LR128GT, M58LR128GB Table 26. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Chip Enable High AVEH t Address Valid to Latch Enable High AVLH t t ...
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Figure 18. Reset and Power-up AC Waveforms tVDHPH VDD, VDDQ Table 27. Reset and Power-up AC Characteristics Symbol Parameter Reset Low to t PLWL Write Enable Low, t PLEL Chip Enable Low, t PLGL Output ...
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M58LR128GT, M58LR128GB PACKAGE MECHANICAL Figure 19. VFBGA56 - 7.7 x 9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 28. VFBGA56 - 7.7 x 9mm - 8x7 ...
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PART NUMBERING Table 29. Ordering Information Scheme Example: Device Type M58 Architecture L = Multi-Level, Multiple Bank, Burst Mode Operating Voltage 1.7V to 2.0V 1.7V to 2.0V DD DDQ Density 128 = 128 Mbit ...
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M58LR128GT, M58LR128GB APPENDIX A. BLOCK ADDRESS TABLES The following set of equations can be used to calculate a complete set of block addresses using the infor- mation contained in Tables 30, 31, 32, 33, 34, and 35. To calculate the ...
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Table 30. M58LR128GT - Parameter Bank Block Addresses Block Size Number (KWords 7D0000-7DFFFF 6 64 7C0000-7CFFFF Table 31. M58LR128GT - ...
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M58LR128GT, M58LR128GB Table 33. M58LR128GB - Parameter Bank Block Addresses Block Size Address Range Number (KWords 070000-07FFFF 9 64 060000-06FFFF 8 64 050000-05FFFF 7 64 040000-04FFFF 6 64 030000-03FFFF 5 64 020000-02FFFF 4 64 010000-01FFFF 3 16 00C000-00FFFF ...
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APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and ...
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M58LR128GT, M58LR128GB Table 38. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 01Bh 0017h bit BCD value in volts bit BCD value in 100 millivolts V ...
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Table 39. Device Geometry Definition Offset Data 027h 0018h Device Size = 2 028h 0001h Flash Device Interface Code description 029h 0000h 02Ah 0006h Maximum number of bytes in multi-byte program or page = 2 02Bh 0000h 02Ch 0002h Number ...
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M58LR128GT, M58LR128GB Table 40. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 10Ah 0050h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” 0049h (P+3)h =10Dh 0031h Major version number, ASCII (P+4)h = 10Eh 0033h Minor version number, ...
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Table 41. Protection Register Information Offset Data Number of protection register fields in JEDEC ID space. 0000h indicates (P+E)h = 118h 0002h that 256 fields are available. (P+F)h = 119h 0080h Protection Field 1: Protection Description Bits 0-7 Lower byte ...
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M58LR128GT, M58LR128GB Table 42. Burst Read Information Offset Data (P+1D)h = 127h 0004h Page-mode read capability bits 0-7 ’n’ such that 2 (P+1E)h = 128h 0004h Number of synchronous mode read configuration fields that follow. (P+1F)h = 129h 0001h Synchronous ...
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Table 44. Bank and Erase Block Region 1 Information Flash memory (top) Flash memory (bottom) Offset Data Offset (P+24)h = 12Eh 0Fh (P+24)h = 12Eh (P+25)h = 12Fh 00h (P+25)h = 12Fh (P+26)h = 130h 11h (P+26)h = 130h (P+27)h ...
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M58LR128GT, M58LR128GB Flash memory (top) Flash memory (bottom) Offset Data Offset (P+38)h = 142h (P+39)h = 143h Note: 1. The variable pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, ...
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Flash memory (top) Flash memory (bottom) Offset Data Offset (P+3F)h = 149h 03h (P+47)h = 151h (P+40)h = 14Ah 03h (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h =14Eh 64h (P+45)h = 14Fh 00h (P+46)h ...
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M58LR128GT, M58LR128GB APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 20. Program Flowchart and Pseudo Code Start Write 40h or 10h (3) Write Address & Data Read Status Register (3) NO SR7 = 1 YES NO SR3 = 0 YES NO ...
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Figure 21. Buffer Program Flowchart and Pseudo Code Start Buffer Program E8h Command, Start Address Read Status Register SR7 = 1 YES (1) Write n Start Address Write Buffer Data, Start Address Write ...
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M58LR128GT, M58LR128GB Figure 22. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) ...
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Figure 23. Block Erase Flowchart and Pseudo Code Start Write 20h (2) Write Block Address & D0h Read Status Register (2) NO SR7 = 1 YES NO SR3 = 0 YES YES SR4, SR5 = SR5 = ...
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M58LR128GT, M58LR128GB Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block or Program/Protection Register ...
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Figure 25. Locking Operations Flowchart and Pseudo Code Start Write 60h (1) Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) End Note: 1. Any address within the bank can ...
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M58LR128GT, M58LR128GB Figure 26. Protection Register Program Flowchart and Pseudo Code Start Write C0h (3) Write Address & Data Read Status Register (3) NO SR7 = 1 YES NO SR3 = 0 YES NO SR4 = 0 YES NO Program ...
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Figure 27. Buffer Enhanced Factory Program Flowchart and Pseudo Code Write 80h to Address WA1 Write D0h to Address WA1 Read Status NO NO Initialize count SR4 = 1 Read Status Register Address WA1 SR3 and SR1for errors Increment Count ...
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M58LR128GT, M58LR128GB APPENDIX D. COMMAND INTERFACE STATE TABLES Table 46. Command Interface States - Modify Table, Next State Program Read Current CI State Setup (2) Array (3,4) (FFh) (10/40h) Program Ready Ready Setup Lock/CR Setup Setup OTP Busy Setup Program ...
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Program Read Current CI State Setup (2) Array (3,4) (FFh) (10/40h) Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N Buffer Program confirm. Else (N Setup Buffer Load 1 Buffer Buffer Program Confirm ...
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M58LR128GT, M58LR128GB Table 47. Command Interface States - Modify Table, Next Output Read Current CI State Array (3) (FFh) Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 ...
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Table 48. Command Interface States - Lock Table, Next State Lock/CR Current CI State (2) Setup (60h) Lock/CR Ready Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy Setup Program Busy Suspend Setup Buffer Load 1 Buffer Buffer Program Confirm ...
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M58LR128GT, M58LR128GB Table 49. Command Interface States - Lock Table, Next Output Lock/CR Current CI State (3) Setup (60h) Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 ...
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REVISION HISTORY Table 50. Document Revision History Date Version 29-Apr-2004 0.1 19-Oct-2004 0.2 31-Jan-2005 0.3 28-June-2005 0.4 Revision Details First Issue. APPENDIX C. revised. Format of APPENDIX A. Lead-Free packages are compliant with the ST ECOPACK specification 12V ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...