ADE3100 STMicroelectronics, ADE3100 Datasheet

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ADE3100

Manufacturer Part Number
ADE3100
Description
LCD Display Engines with Integrated DVI, ADC and YUV Ports
Manufacturer
STMicroelectronics
Datasheet

Specifications of ADE3100

Case
QFP

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The ADE3xxx is a family of highly integrated display engine ICs, enabling the most advanced, flexible, and
cost-effective system-on-chip solutions for LCD display applications. The ADE3xxx line-up covers the full
range of applications from XGA analog only to dual SXGA Smart Panel designs. All twelve ADE3xxx
devices are pin-to-pin compatible and use a common software platform.
Feature Overview
Product Selector
October 2003
ADE3000
ADE3000T
ADE3000SX
ADE3000SXT
ADE3050
ADE3050T
ADE3050SX
ADE3050SXT
ADE3100
ADE3200
ADE3250
ADE3300
Programmable Context Sensitive™ Scaling
High-quality up-scaling and down-scaling
Dual Input: DVI / VGA
Integrated 9-bit ADC/PLL
Integrated DVI-Rx
IQSync™ AutoSetup
Integrated programmable timing controller
Integrated Pattern generator
Perfect Picture™ Technology
sRGB 3D Color Warp
Integrated OSD
Product
®
Analog
x
x
x
x
x
x
x
x
Input Interface Support
DVI
x
x
x
x
x
x
x
x
with Integrated DVI, ADC and YUV Ports
YUV
x
x
x
x
x
x
x
x
x
x
x
x
ADE3000 ADE3050 ADE3100
ADE3200 ADE3250 ADE3300
Advanced EMI reduction features
Framelock operation with Safety Mode™
Serial I²C interface
Low power 0.18 µm process technology
208-pin PQFP Package
Up to XGA 75Hz
Up to XGA 75Hz
Up to SXGA 75Hz
Up to SXGA 75Hz
Up to XGA 75Hz
Up to XGA 75Hz
Up to SXGA 75Hz
Up to SXGA 75Hz
Up to XGA 75Hz
Up to XGA 75Hz
Up to SXGA 75Hz
Up to SXGA 75Hz
LCD Display Engines
Resolution
Output Format Support
TCON
x
x
x
x
x
x
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Related parts for ADE3100

ADE3100 Summary of contents

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... ADE3050SXT x ADE3100 x ADE3200 x ADE3250 x ADE3300 October 2003 ADE3000 ADE3050 ADE3100 ADE3200 ADE3250 ADE3300 with Integrated DVI, ADC and YUV Ports Advanced EMI reduction features Framelock operation with Safety Mode™ Serial I²C interface Low power 0.18 µm process technology DVI YUV x ...

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Third Generation Context Sensitive™ Scaler Sharper text with Edge Enhancement RAM based coefficients for unique customization 5:1 upscale and 2:1 downscale Independent axis zoom and shrink Bob de-interlacing eliminates jaggies and motion artifacts Analog RGB input 140MHz ...

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ADE3XXX Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SRGB Block ........................................................................................................................64 2.18.1 Parametric Gamma Correction and Digital Contrast/Brightness Control .......................................... 64 2.18.2 Color Space Warp ............................................................................................................................. 64 2.19 OSD Block ..........................................................................................................................66 2.20 Flicker Block .......................................................................................................................72 2.21 Gamma Block .....................................................................................................................74 2.22 APC Block ..........................................................................................................................74 2.23 Output Mux Block ...

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ADE3XXX 1 General Description YUV Port DMEAS Analog Port SMEAS DVI Port DATA LLKPLL CTRL The ADE3XXX family of devices is capable of implementing all of the advanced features of today’s LCD monitor products. For maximum flexibility, an external microcontroller ...

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Pin Description Feature Sync / Timing Once an input source is selected, all available information on frequencies and Measurement line/pixel counts is measured for the selected source and made available to the MCU. Mode Set Once the MCU has determined ...

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ADE3XXX Pin # Name 6 YUV1 7 YUV0 8 YUVCLK 9 DVDD18 10 DGND 11 DVDD18 12 DGND 13 AGND 14 AVDD18 15 AVDD33 16 RX2M 17 RX2P 18 AGND 19 AVDD33 20 RX1M 21 RX1P 22 AVDD33 23 RX0M ...

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Pin Description Pin # Name 45 AGND 46 AVDD18 47 XGND 48 XTAL_IN 49 XTAL_OUT 50 XVDD18 51 LVDD18 52 LGND 53 CSYNC 54 VSYNC 55 HSYNC 56 AGND 57 AGND 58 AVDD33 59 AVDD33 60 AGND 61 AVDD18 62 ...

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ADE3XXX Pin # Name 84 AGND 85 AVDD18 86 AVDD18 87 REFR 88 REFMR 89 REFPR 90 AGND 91 AGND 92 INR 93 AVDD33 94 AVDD33 95 REFCR 96 AGND 97 AVDD18 98 AVDD18 99 TST_SCAN 100 DGND 101 DVDD33 ...

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Pin Description Pin # Name 123 DVDD18 124 DGND 125 DVDD33 126 ORA7 127 ORA6 128 ORA5 129 ORA4 130 ORA3 131 ORA2 132 ORA1 133 ORA0 134 DVDD33 135 DGND 136 ODE 137 OHS 138 OCLK 139 OVS 140 ...

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ADE3XXX Pin # Name 162 OGB1 163 OGB0 164 DVDD18 165 DGND 166 DVDD18 167 DGND 168 ORB7 169 ORB6 170 ORB5 171 ORB4 172 DVDD33 173 DGND 174 ORB3 175 ORB2 176 ORB1 177 ORB0 178 DVDD18 179 DGND ...

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Pin Description Pin # Name 201 DVDD18 202 DGND 203 SCL 204 SDA 205 XCLK 206 XCLK_EN 207 RESETN 208 YUV7 12/88 Table 2: Pin Description (Sheet Type Power Digital 1.8V VDD Power Digital Ground Input I2C ...

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ADE3XXX 2 ADE3XXX Functional Description 2.1 Global Control Block The global control block is responsible for: Selecting Clock Sources Power Control I²C Control SCLK Frequency Synthesizer Control Block-by-Block Synchronous Reset Generation The global control block runs on the XCLK clock ...

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Global Control Block MD = INT(f XCLK INT(( ( where f is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency XCLK generated by this block is f ...

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ADE3XXX Register Name GLBL_CLK_SRC_SEL_2 GLBL_CLK_INV GLBL_ANA_PWR GLBL_XK_SRST GLBL_I2C_CTRL GLBL_XTAL_CTRL Table 4: Global Registers (Sheet Addr. Mode Bits Default 0x0002 [7] 0x0 R/W [6:4] 0x4 [3] R/W [2:0] 0x4 0x0003 [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 ...

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Global Control Block Register Name GLBL_SCLK_SYNTH_CTRL GLBL_SCLK_MD_SD GLBL_SCLK_PE_L GLBL_SCLK_PE_H GLBL_TST_CTRL GLBL_ADC_CLK_SRC_SEL GLBL_SCLK_CTRL GLBL_TCON_BPAD_EN 16/88 Table 4: Global Registers (Sheet Addr. Mode Bits Default 0x0009 [7:5] 0x0 R/W [4:3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] ...

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ADE3XXX Register Name GLBL_CLK_SRC_SEL_3 GLBL_IK_SRST GLBL_DK_SRST 2.2 FM Frequency Synthesizer The FM frequency synthesizer creates a clock equivalent eight times the crystal input clock, using a digital frequency synthesizer. The modulation period and amplitude are directly controlled ...

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ADC Block where f and f OUT XCLK The maximum output frequency of the fm frequency synthesizer is f Note that native duty cycle of the fm frequency synthesizer is not 50/50. We recommend to either enable the divide-by-two in ...

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ADE3XXX 2.4 Line Lock PLL Block The line lock PLL recovers a sample clock from an incoming hsync source. The response characteristics of the line lock PLL are adjustable for optimimum response time and jitter filtering. The phase of the ...

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Line Lock PLL Block Register Name LLK_PLL_CTRL LLK_PLL_MFACTOR_L LLK_PLL_MFACTOR_H LLK_PLL_HPERIOD_L LLK_PLL_HPERIOD_H LLK_PLL_PHASE_RATE_INIT_0 LLK_PLL_PHASE_RATE_INIT_1 LLK_PLL_PHASE_RATE_INIT_2 LLK_PLL_PHASE_RATE_INIT_3 LLK_PLL_PHASE_RATE_INIT_WR LLK_PLL_TC_AEF LLK_PLL_TC_BEF LLK_PLL_TC_ALF LLK_PLL_TC_BLF LLK_PLL_TC_AES LLK_PLL_TC_BES LLK_PLL_TC_ALS 20/88 Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x0801 R/W [7:6] ...

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ADE3XXX Register Name LLK_PLL_TC_BLS LLK_PLL_TC_AEK LLK_PLL_TC_BEK LLK_PLL_TC_ALK LLK_PLL_TC_BLK LLK_PLL_TC_SLOW_TOL LLK_PLL_TC_SLOW_LINE_NB LLK_PLL_LOCK_TOL LLK_PLL_LOCK_LINE_NB LLK_PLL_PH_OFFSET LLK_PLL_PH_OFFSET_EN LLK_PLL_PULSE_HIGH_EXT LLK_PLL_STAT_LINES_L LLK_PLL_STAT_LINES_H LLK_PLL_STAT_ERROR_INC_LOW 0x0820 Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x0812 [7:6] R/W [5:0] 0x0813 [7:4] R/W [3:0] ...

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Digital Video Input (DVI) Register Name LLK_PLL_UPDATE LLK_PLL_STATUS LLK_PLL_PH_ERROR_L LLK_PLL_PH_ERROR_H LLK_PLL_PHASE_RATE_0 LLK_PLL_PHASE_RATE_1 LLK_PLL_PHASE_RATE_2 LLK_PLL_PHASE_RATE_3 LLK_PLL_PHASE_RATE_I_0 LLK_PLL_PHASE_RATE_I_1 LLK_PLL_PHASE_RATE_I_2 LLK_PLL_PHASE_RATE_I_3 LLK_PLL_STAT_ERROR_MEAN LLK_PLL_STAT_ERROR_PP_L LLK_PLL_STAT_ERROR_PP_H LLK_PLL_STAT_ERROR_ABS_L LLK_PLL_STAT_ERROR_ABS_H LLK_PLL_STAT_ERROR_GTX 2.5 Digital Video Input (DVI) The DVI receiver has the following features: compatible with all DVI ...

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ADE3XXX Recommended values for best receiver quality are given in the following table MHz MHz 61 to 100 MHz 101 to 140 MHz Register Name DVI_ACCUM_CONST DVI_EXT_SHIFT_CNT DVI_EXT_SHIFT_CNT_ENAB DVI_INVALID_L DVI_INVALID_C DVI_INVALID_R Table 8: Recommended ...

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Digital Video Input (DVI) Register Name DVI_INVALID_SEL_EN DVI_ERROR_SKEW_EN DVI_LCR0_1 DVI_LCR2_3 DVI_LCR4_5 DVI_LCR6_7 DVI_LCR_RV_EN DVI_TEST_SEL DVI_PLL_0 24/88 Table 9: DVI Registers (Sheet Addr Mode Bits Default 0x0407 R/W [7:3] R/W [2:1] 0x0 R/W [0] 0x0 0x0408 R/W [7:3] ...

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ADE3XXX Register Name DVI_PLL_0 DVI_PLL_1 DVI_PLL_2 Table 9: DVI Registers (Sheet Addr Mode Bits Default 0x0480 R/W [7] R/W [6:5] 0x0 R/W [4:3] 0x0 R/W [2:0] 0x0 0x0481 R/W [7] 0x0 R/W [6:5] 0x0 R/W [4:1] 0x0 ...

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Digital Video Input (DVI) Register Name DVI_PLL_3 DVI_PLL_4 DVI_PLL_5 DVI_PLL_6 DVI_PLL_7 DVI_PLL_8 DVI_PLL_2 DVI_PLL_3 DVI_PLL_4 DVI_PLL_5 26/88 Table 9: DVI Registers (Sheet Addr Mode Bits Default 0x0483 R/W [7:6] 0x0 R/W [5:4] 0x0 R/W [3:2] 0x0 R/W ...

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ADE3XXX Register Name DVI_PLL_6 DVI_PLL_7 DVI_PLL_8 DVI_PLL_9 DVI_PLL_10 2.6 HDCP Block The HDCP block implements the datapath decryption block of the HDCP content protection scheme of DVI. Please refer to the HDCP Specification 1.0 for details. The state machines of ...

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HDCP Block Register Name HDCP_STATUS HDCP_CTRL HDCP_AN0 HDCP_AN1 HDCP_AN2 HDCP_AN3 HDCP_AN4 HDCP_AN5 HDCP_AN6 HDCP_AN7 HDCP_KM0 HDCP_KM1 HDCP_KM2 HDCP_KM3 HDCP_KM4 HDCP_KM5 HDCP_KM6 HDCP_R_L HDCP_R_H 28/88 Table 10: HDCP Registers Addr Mode Bits Default 0x0500 [7:3] 0x0 R [2:0] 0x0 0x0501 R/W ...

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ADE3XXX 2.7 YUV Block The TV video input module is used to interface external TV video decoder chip. It handles VESA Video Interface Port(VIP) 8-bit/16-bit YC and double clock edge input RGB data formats. It extracts embedded sync timing and ...

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Sync Retiming Block Register Name YUV_INT 2.8 Sync Retiming Block The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, SRT has the following functionality: Retimes ...

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ADE3XXX Register Name SRTXK_VSYNC_SEL SRTXK_VSYNC_THR_L SRTXK_VSYNC_THR_H SRTXK_COAST_VS_SEL SRTXK_COAST_RISE_L SRTXK_COAST_RISE_M SRTXK_COAST_RISE_H SRTXK_COAST_FALL_L SRTXK_COAST_FALL_M SRTXK_COAST_FALL_H SRTIK_HS_CTRL SRTIK_VS_SEL Table 12: Sync Retiming Registers (Sheet Addr Mode Bits 0x01E5 R/W [7:3] [2:0] 0x01E6 R/W [7:0] 0x01E7 R/W [7:4] R/W [3:0] 0x01E8 ...

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Sync Measurement Block 2.9 Sync Measurement Block The Input Sync Measurement Block (SMEAS) continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the ...

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ADE3XXX Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_CLEAR SMEAS_H_CTRL Addr Mode Bits Default 0x0110 [7:3] R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0111 [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] ...

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Sync Measurement Block Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_V_CTRL SMEAS_H_SEL 34/88 Addr Mode Bits Default 0x0112 [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W ...

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ADE3XXX Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_V_SEL SMEAS_STATUS_MASK SMEAS_H_NUM_LINES SMEAS_H_SKIP_L SMEAS_H_SKIP_H Addr Mode Bits Default 0x0114 R/W [7:4] 0x0 R/W [3:0] 0x0 0x0119 R/W [7] 0x0 R/W [6] 0x0 [5:4] R/W [3] 0x0 R/W ...

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Sync Measurement Block Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_SKEW_CTRL SMEAS_SKEW_THRES SMEAS_DELAY_VSYNC SMEAS_REF_XK_PER_H_L SMEAS_REF_XK_PER_H_M SMEAS_REF_XK_PER_H_H SMEAS_REF_XK_PER_V_L SMEAS_REF_XK_PER_V_M SMEAS_REF_XK_PER_V_H SMEAS_REF_H_PER_V_L SMEAS_REF_H_PER_V_H SMEAS_REF_XK_V_PER_HI_L SMEAS_REF_XK_V_PER_HI_M SMEAS_REF_XK_V_PER_HI_H SMEAS_REF_POLARITY SMEAS_XK_HTOL_EXP SMEAS_XK_VTOL_EXP SMEAS_HSYNC_VTOL SMEAS_FILTR_HS_WIDTH SMEAS_ACT_POLLING 36/88 Addr Mode Bits Default 0x011D ...

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ADE3XXX Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_ANA_ACT SMEAS_DVI_ACT SMEAS_YUV_ACT SMEAS_ANA_STUCK SMEAS_DVI_STUCK SMEAS_YUV_STUCK SMEAS_XK_PER_H_L SMEAS_XK_PER_H_M SMEAS_XK_PER_H_H SMEAS_XK_PER_V_L SMEAS_XK_PER_V_M SMEAS_XK_PER_V_H Addr Mode Bits Default 0x0140 [7:5] 0x0 R [4] 0x0 R [3] 0x0 R [2] 0x0 ...

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Sync Measurement Block Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_H_PER_V_L SMEAS_H_PER_V_H SMEAS_SK_V_HI_L SMEAS_SK_V_HI_M SMEAS_SK_V_HI_H SMEAS_TIMEOUT_STATUS SMEAS_STATUS_RANGE SMEAS_MEAS_POLLING 38/88 Addr Mode Bits Default 0x014C R [7:0] 0x0 0x014D R [7:0] 0x0 0x014E R [7:0] 0x0 0x014F ...

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ADE3XXX Table 13: Sync Measurement Registers (Sheet Register Name SMEAS_SKEW_STATUS SMEAS_V_OUTOF_RNG SMEAS_H_OUTOF_RNG SMEAS_HV_OUTOF_RNG SMEAS_VHI_OUTOF_RNG SMEAS_HPOL_OUTOF_RNG SMEAS_VPOL_OUTOF_RNG Addr Mode Bits Default 0x0154 [7:2] 0x0 R [1] 0x0 R [0] 0x0 0x0155 R [7:0] 0x0 0x0156 R [7:0] 0x0 ...

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Sync Mux Block 2.10 Sync Mux Block The Sync Mux (SMUX) block provides the following functions: selects between all possible sync signals generates missing sync signals selects between original and generated signals for output generates the clamp signal for the ...

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ADE3XXX Register Name SMUX_CTRL2 SMUX_CLAMP_SET_L SMUX_CLAMP_SET_H SMUX_CLAMP_RST_L SMUX_CLAMP_RST_H SMUX_HENAB_SET_L SMUX_HENAB_SET_H SMUX_HENAB_RST_L SMUX_HENAB_RST_H SMUX_VENAB_SET_L SMUX_VENAB_SET_H SMUX_VENAB_RST_L SMUX_VENAB_RST_H SMUX_HSYNC_PHASE SMUX_VSYNC_PHASE Table 14: Sync Mux Registers (Sheet Addr Mode Bits Default 0x0202 R [7] 0x0 R/W [6] 0x0 R/W [5:4] ...

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Data Mux Block 2.11 Data Mux Block Data mux provides the following functions: selection of one among three data sources debug modes (e.g. bit order swap, color swap) Register DMUX_CHANSEL 2.12 Data Measurement Block The Data Measurement module measures several ...

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ADE3XXX In One-shot mode, the block indicates that measurement is valid through an auto-clear of start condition. In Free-running mode, the block indicates that measurement is valid through a polling bit. In Free- running mode, a freeze bit is provided ...

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Data Measurement Block The first and last pixels are measured for each line, and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. The intention is that "last data ...

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ADE3XXX Table 16: Data Measurement Registers (Sheet Register Name DMEAS_COLOR_CTRL DMEAS_THR_PHM_EDGE DMEAS_THR_DMM DMEAS_WIN_PHM_MINX_L DMEAS_WIN_PHM_MINX_H DMEAS_WIN_PHM_MAXX_L DMEAS_WIN_PHM_MAXX_H DMEAS_WIN_PHM_MINY_L DMEAS_WIN_PHM_MINY_H DMEAS_WIN_PHM_MAXY_L DMEAS_WIN_PHM_MAXY_H DMEAS_WIN_DMM_MINX_L DMEAS_WIN_DMM_MINX_H DMEAS_WIN_DMM_MAXX_L DMEAS_WIN_DMM_MAXX_H DMEAS_WIN_DMM_MINY_L Addr Mode Bits Default 0x0901 [7:4] R/W [3:2] 0x0 R/W [1:0] 0x0 ...

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Data Measurement Block Table 16: Data Measurement Registers (Sheet Register Name DMEAS_WIN_DMM_MINY_H DMEAS_WIN_DMM_MAXY_L DMEAS_WIN_DMM_MAXY_H DMEAS_PHM_EDGESEL DMEAS_DMM_EDGESEL DMEAS_PHM_MODE_CTRL 46/88 Addr Mode Bits Default 0x0911 [7:4] R/W [3:0] 0x0912 R/W [7:0] 0xFFF 0x0913 [7:4] R/W [3:0] 0x0914 [7:2] 0xFFF ...

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ADE3XXX Table 16: Data Measurement Registers (Sheet Register Name DMEAS_DMM_MODE_CTRL DMEAS_DMM_DE_REF_L DMEAS_DMM_DE_REF_H DMEAS_DMM_DE_TOL DMEAS_DMM_DE_RST DMEAS_DATA_PHM_EDGE0 DMEAS_DATA_PHM_EDGE1 DMEAS_DATA_PHM_EDGE2 DMEAS_DATA_PHM_EDGE3 DMEAS_DATA_PHM_PSUM0 DMEAS_DATA_PHM_PSUM1 DMEAS_DATA_PHM_PSUM2 DMEAS_DATA_PHM_PSUM3 DMEAS_DATA_DMM_MIN DMEAS_DATA_DMM_MAX Addr Mode Bits Default 0x0917 R/W [7] 0x0 R/W [6] 0x0 R/W [5] ...

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Programmable Nonlinearity Block Table 16: Data Measurement Registers (Sheet Register Name DMEAS_DATA_DMM_PCD_L DMEAS_DATA_DMM_PCD_M DMEAS_DATA_DMM_PCD_H DMEAS_DATA_DMM_HPOSMIN_L DMEAS_DATA_DMM_HPOSMIN_H DMEAS_DATA_DMM_HPOSMAX_L DMEAS_DATA_DMM_HPOSMAX_H 0x092C DMEAS_DATA_DMM_VPOSMIN_L DMEAS_DATA_DMM_VPOSMIN_H DMEAS_DATA_DMM_VPOSMAX_L DMEAS_DATA_DMM_VPOSMAX_H 0x0930 DMEAS_DATA_DMM_SIZE_L DMEAS_DATA_DMM_SIZE_H DMEAS_DATA_DMM_DE_STATUS DMEAS_SCR_PAD_0 DMEAS_SCR_PAD_1 DMEAS_SCR_PAD_2 DMEAS_SCR_PAD_3 DMEAS_SCR_PAD_4 DMEAS_SCR_PAD_5 DMEAS_SCR_PAD_6 DMEAS_SCR_PAD_7 DMEAS_SCR_PAD_8 DMEAS_SCR_PAD_9 ...

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ADE3XXX PNL block to the LCD gamma value, then the post-scaler gamma RAM implements the corresponding inverse gamma function. Register Name PNL_CTRL 2.14 Scaler Block The scale module resizes images from one resolution to another. For this, a 3x3 non-separable ...

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Scaler Block Register Name SCL_THRES_OFFSET_L SCL_THRES_OFFSET_H SCL_CBBYPASS SCL_CON_CAL_SEL SCL_TESTCON SCL_LUT1 SCL_LUT2 SCL_LUT3 SCL_LUT4 SCL_LUT5 SCL_LUT6 SCL_LUT7 SCL_LUT8 SCL_LUT9 SCL_LUT10 SCL_LUT11 SCL_LUT12 SCL_LUT13 SCL_LUT14 50/88 Table 18: Scaler Block Registers (Sheet Addr Mode Bits 0x0A13 R/W [7:0] 0x0A14 ...

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ADE3XXX Register Name SCL_LUT15 SCL_BGCOLOR_R SCL_BGCOLOR_G SCL_BGCOLOR_B SCL_BCOLOR_CTRL SCL_AVERAGE_IK SCL_FLIP_H_IK Table 18: Scaler Block Registers (Sheet Addr Mode Bits 0x0A26 R/W [7:0] 0x0A27 R/W [7:0] 0x0A28 R/W [7:0] 0x0A29 R/W [7:0] 0x0A2A R/W [7] R/W [6] R/W ...

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Output Sequencer Block 2.15 Output Sequencer Block The output sequencer module provides timing for the output video interface. It allows sufficient flexibility to support a broad range of Smart Panel applications as well. The timing unit is based on horizontal ...

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ADE3XXX Table 19: Output Sequencer Registers (Sheet Register Name OSQ_CONTROL OSQ_CLOCK_FRAC OSQ_OUT_HTOTAL_L OSQ_OUT_HTOTAL_H OSQ_OUT_VTOTAL_MIN_L OSQ_OUT_VTOTAL_MIN_H OSQ_VTOTAL_MAX_L OSQ_VTOTAL_MAX_H OSQ_VERTEN_DLY_E_L OSQ_VERTEN_DLY_E_M OSQ_VERTEN_DLY_E_H OSQ_VERTEN_DLY_O_L OSQ_VERTEN_DLY_O_M Addr Mode Bits Default 0x0BC1 R [7] R/W [6] 0x0 R/W [5] 0x0 R/W [4] ...

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Output Sequencer Block Table 19: Output Sequencer Registers (Sheet Register Name OSQ_VERTEN_DLY_O_H OSQ_VSYNC_SET_L OSQ_VSYNC_SET_H OSQ_VSYNC_RST_L OSQ_VSYNC_RST_H OSQ_HSYNC_SET_L OSQ_HSYNC_SET_H OSQ_HSYNC_RST_L OSQ_HSYNC_RST_H OSQ_HENAB_SET_L OSQ_HENAB_SET_H OSQ_HENAB_RST_L OSQ_HENAB_RST_H OSQ_VENAB_SET_L OSQ_VENAB_SET_H OSQ_VENAB_RST_L OSQ_VENAB_RST_H OSQ_OUT_VCOUNT 54/88 Addr Mode Bits Default 0x0BCE [7:4] 0x0 ...

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ADE3XXX 2.16 Timing Controller (TCON) Block The Output Timing Controller module provides timing for Smart Panel applications. The timing unit is based on horizontal and vertical counters locked with the output video stream. A set of programmable comparators provides all ...

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Timing Controller (TCON) Block Register Name TCON_COMP_7_L TCON_COMP_7_H TCON_COMP_8_L TCON_COMP_8_H TCON_COMP_9_L TCON_COMP_9_H TCON_COMP_10_L TCON_COMP_10_H TCON_COMP_11_L TCON_COMP_11_H TCON_COMP_12_L TCON_COMP_12_H TCON_COMP_13_L TCON_COMP_13_H TCON_COMP_14_L TCON_COMP_14_H TCON_COMP_15_L TCON_COMP_15_H TCON_COMP_16_L TCON_COMP_16_H TCON_COMP_17_L TCON_COMP_17_H TCON_COMP_18_L TCON_COMP_18_H TCON_COMP_19_L TCON_COMP_19_H TCON_COMP_20_L TCON_COMP_20_H TCON_COMP_21_L TCON_COMP_21_H TCON_COMP_22_L TCON_COMP_22_H TCON_COMP_23_L TCON_COMP_23_H ...

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ADE3XXX Register Name TCON_COMP_26_L TCON_COMP_26_H TCON_COMP_27_L TCON_COMP_27_H TCON_SRTD_0 TCON_SRTD_1 TCON_SRTD_2 TCON_SRTD_3 TCON_SRTD_4 TCON_SRTD_5 TCON_SRTD_6 TCON_SRTD_7 TCON_SRTD_8 TCON_SRTD_9 TCON_SRTD_10 TCON_SRTD_11 TCON_SRTD_12 TCON_SRTD_13 TCON_SRTD_14 TCON_SRTD_15 TCON_SRTD_16 TCON_SRTD_17 TCON_SRTD_18 TCON_SRTD_19 TCON_SRTD_20 TCON_SRTD_21 TCON_SRTD_22 TCON_SRTD_23 TCON_SRTD_24 TCON_SRTD_25 TCON_SRTD_26 Table 20: TCON Registers (Sheet 3 ...

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Timing Controller (TCON) Block Register Name TCON_SRTD_27 TCON_SRTD_28 TCON_SRTD_29 TCON_SRTD_30 TCON_SRTD_31 TCON_X_0 TCON_X_1 TCON_X_2 TCON_X_3 TCON_X_4 TCON_X_5 TCON_X_6 TCON_X_7 TCON_X_8 TCON_X_9 TCON_X_10 TCON_X_11 TCON_X_12 TCON_X_13 TCON_X_14 TCON_X_15 TCON_X_16 TCON_X_17 TCON_X_18 TCON_X_19 TCON_X_20 58/88 Table 20: TCON Registers (Sheet 4 of ...

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ADE3XXX Register Name TCON_X_21 TCON_X_22 TCON_X_23 TCON_X_24 TCON_X_25 TCON_X_26 TCON_X_27 TCON_X_28 TCON_X_29 TCON_X_30 TCON_X_31 TCON_X_32 TCON_X_33 TCON_X_34 TCON_X_35 TCON_X_36 TCON_X_37 TCON_X_38 TCON_X_39 TCON_X_40 TCON_X_41 TCON_X_42 TCON_X_43 TCON_X_44 TCON_X_45 TCON_X_46 TCON_X_47 TCON_X_48 TCON_X_49 TCON_X_50 TCON_X_51 TCON_X_52 TCON_X_53 TCON_X_54 Table 20: TCON ...

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Pattern Generator Block Register Name TCON_X_55 TCON_X_56 TCON_X_57 TCON_X_58 TCON_X_59 TCON_X_60 TCON_X_61 TCON_X_62 TCON_X_63 1. Refer to register TCON_X_O for definition. 2.17 Pattern Generator Block The integrated Pattern Generator displays a set of graphic patterns to help debugging systems and ...

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ADE3XXX When the programmed block size corresponds to a larger 8x8 grid than the total screen area, only the blocks or part of blocks included in the output screen space are rendered. The 8x8 block set is upper left justified. ...

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Pattern Generator Block Register Name PGEN_P0_MODE PGEN_P1_MODE PGEN_P0_WIDTH_X_L PGEN_P0_WIDTH_X_H PGEN_P0_WIDTH_X_OFFSET_L PGEN_P0_WIDTH_X_OFFSET_H PGEN_P0_HEIGHT_Y_L PGEN_P0_HEIGHT_Y_H PGEN_P0_HEIGHT_Y_OFFSET_L PGEN_P0_HEIGHT_Y_OFFSET_H PGEN_P1_WIDTH_X_L PGEN_P1_WIDTH_X_H PGEN_P1_WIDTH_X_OFFSET_L PGEN_P1_WIDTH_X_OFFSET_H PGEN_P1_HEIGHT_Y_L PGEN_P1_HEIGHT_Y_H PGEN_P1_HEIGHT_Y_OFFSET_L PGEN_P1_HEIGHT_Y_OFFSET_H PGEN_P0_COLOR_R_C0 PGEN_P0_COLOR_G_C0 PGEN_P0_COLOR_B_C0 PGEN_P0_COLOR_R_C1 PGEN_P0_COLOR_G_C1 62/88 Table 21: PGEN Registers (Sheet Addr Mode Bits ...

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ADE3XXX Register Name PGEN_P0_COLOR_B_C1 PGEN_P1_COLOR_R_C0 PGEN_P1_COLOR_G_C0 PGEN_P1_COLOR_B_C0 PGEN_P1_COLOR_R_C1 PGEN_P1_COLOR_G_C1 PGEN_P1_COLOR_B_C1 PGEN_P0_GRADDELTA_R PGEN_P0_GRADDELTA_G PGEN_P0_GRADDELTA_B PGEN_P0_GRADSTEP_X PGEN_P0_GRADSTEP_Y PGEN_P1_GRADDELTA_R PGEN_P1_GRADDELTA_G PGEN_P1_GRADDELTA_B PGEN_P1_GRADSTEP_X PGEN_P1_GRADSTEP_Y PGEN_P0_SEQ_COL0_COL1 PGEN_P0_SEQ_COL2_COL3 PGEN_P0_SEQ_COL4_COL5 PGEN_P0_SEQ_COL6_COL7 PGEN_P1_SEQ_COL0_COL1 PGEN_P1_SEQ_COL2_COL3 PGEN_P1_SEQ_COL4_COL5 Table 21: PGEN Registers (Sheet Addr Mode Bits Default 0x0628 ...

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SRGB Block Register Name PGEN_P1_SEQ_COL6_COL7 PGEN_B_TOP_BOTTOM PGEN_B_LEFT_RIGHT PGEN_X_TOTAL_L PGEN_X_TOTAL_H PGEN_Y_TOTAL_L PGEN_Y_TOTAL_H 2.18 SRGB Block The sRGB block performs two primary functions: 1. Parametric gamma correction on multiple windows or full screen for video enhancement in a window and digital contrast/brightness ...

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ADE3XXX Register Name SRGB_CTRL SRGB_BLACK_R SRGB_BLACK_G SRGB_BLACK_B SRGB_RED_R SRGB_RED_G SRGB_RED_B SRGB_GREEN_R SRGB_GREEN_G SRGB_GREEN_B SRGB_BLUE_R SRGB_BLUE_G SRGB_BLUE_B SRGB_YELLOW_R SRGB_YELLOW_G SRGB_YELLOW_B SRGB_CYAN_R Figure 8: Color Space Warp Color Space Warp IN OUT Table 22: SRGB Registers (Sheet Addr Mode ...

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OSD Block Register Name SRGB_CYAN_G SRGB_CYAN_B SRGB_MAGENTA_R SRGB_MAGENTA_G SRGB_MAGENTA_B SRGB_WHITE_R SRGB_WHITE_G SRGB_WHITE_B SRGB_GAMMA_A_RED_A SRGB_GAMMA_A_RED_B SRGB_GAMMA_A_RED_C SRGB_GAMMA_A_GREEN_A SRGB_GAMMA_A_GREEN_B SRGB_GAMMA_A_GREEN_C SRGB_GAMMA_A_BLUE_A SRGB_GAMMA_A_BLUE_B SRGB_GAMMA_A_BLUE_C SRGB_GAMMA_B_RED_A SRGB_GAMMA_B_RED_B SRGB_GAMMA_B_RED_C SRGB_GAMMA_B_GREEN_A SRGB_GAMMA_B_GREEN_B SRGB_GAMMA_B_GREEN_C SRGB_GAMMA_B_BLUE_A SRGB_GAMMA_B_BLUE_B SRGB_GAMMA_B_BLUE_C 2.19 OSD Block Introduction The integrated on-screen display (OSD) controller ...

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ADE3XXX Graphics character attributes: per-pixel color, vertical/horizontal mirroring Row attributes: double width, double height Window attributes: window visibility, position, size, border shadow, color table Global attributes: OSD visibility, OSD screen position, alpha fade in/fade out, global size doubling, rotation in ...

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OSD Block effects. An alpha value of 255 makes the OSD opaque, while a value of 0 makes the OSD invisible, with a linear ramp of transparency between these two endpoints. Separate registers control alpha for foreground and background pixels. ...

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ADE3XXX and the primary color (red, green, or blue). The data byte following the second header byte is written to the selected (table, index, primary) location. Font Data Font data is sent to the OSD through burst transfers. The first ...

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OSD Block Table 24: OSD Attribute Map Definition (Sheet Row 70/88 Column Bits ...

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ADE3XXX Table 24: OSD Attribute Map Definition (Sheet Row Column Bits ...

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Flicker Block Register Name OSD_PORT 2.20 Flicker Block The Flicker block computes correlations of the image data with potential inversion patterns of the LCD which in turn allows the microcontroller to modify the polarity signal to cancel large area flicker. ...

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ADE3XXX Register Name FLK_FRAME_CNT_MAX FLK_MEAS0_0 FLK_MEAS0_1 FLK_MEAS0_2 FLK_MEAS0_3 FLK_MEAS1_0 FLK_MEAS1_1 FLK_MEAS1_2 FLK_MEAS1_3 FLK_MEAS2_0 FLK_MEAS2_1 FLK_MEAS2_2 FLK_MEAS2_3 FLK_MEAS3_0 FLK_MEAS3_1 FLK_MEAS3_2 FLK_MEAS3_3 FLK_MEAS4_0 FLK_MEAS4_1 FLK_MEAS4_2 FLK_MEAS4_3 FLK_MEAS5_0 FLK_MEAS5_1 FLK_MEAS5_2 FLK_MEAS5_3 FLK_MEAS6_1 FLK_MEAS6_2 FLK_MEAS6_3 FLK_MEAS6_4 Table 26: Flicker Registers (Sheet ...

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Gamma Block Register Name FLK_MEAS7_0 FLK_MEAS7_1 FLK_MEAS7_2 FLK_MEAS7_3 2.21 Gamma Block The Gamma block performs an 8 bit to 10 bit lookup table on the bits ( color data coming from SCALER. Register Name GAMMA_CTRL ...

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ADE3XXX Register Name APC_APC0 APC_APC1 2.23 Output Mux Block Register Name OMUX_CTRL_0 OMUX_CTRL_1 Table 28: APC Registers Addr Mode Bits 0x0C20 [7] R/W [6:5] 0x0 R/W [4:1] 0x0 R/W [0] 0x0 0x0C21 [7:2] R/W [1] 0x0 R/W [0] 0x0 Table ...

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Output Mux Block Register Name OMUX_CTRL_2 OMUX_DLY_BA0 OMUX_ DLY_BA2 OMUX_ DLY_BA4 OMUX_ DLY_BA6 OMUX_ DLY_GA0 OMUX_ DLY_GA2 OMUX_ DLY_GA4 OMUX_ DLY_GA6 OMUX_ DLY_RA0 OMUX_ DLY_RA2 OMUX_ DLY_RA4 OMUX_ DLY_RA6 OMUX_ DLY_BB0 OMUX_ DLY_BB2 OMUX_ DLY_BB4 OMUX_ DLY_BB6 OMUX_ DLY_GB0 OMUX_ ...

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ADE3XXX Register Name OMUX_ DLY_GB4 OMUX_ DLY_GB6 OMUX_ DLY_RB0 OMUX_ DLY_RB2 OMUX_ DLY_R_B4 OMUX_ DLY_R_B6 OMUX_ DLY_TCON_0 OMUX_ DLY_TCON_2 OMUX_ DLY_TCON_4 OMUX_ DLY_TCON_6 OMUX_ DLY_VS_ENAB OMUX_ DLY_CLK_HS OMUX_CTRL_3 OMUX_REFCOUNT 2.24 Pulse Width Modulation (PWM) Block The PWM B block generates ...

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Pulse Width Modulation (PWM) Block Register Name PWM_CTRL0 PWM_CTRL1 PWM_PERIOD_L PWM_PERIOD_H PWM_DUTY_L PWM_DUTY_H PWM_OVERLAP_L PWM_OVERLAP_H PWM_STEP_DELAY PWM_CYCLES_PER_FRAME_L PWM_CYCLES_PER_FRAME_H 78/88 Table 30: PWM Registers Addr Mode Bits Default 0x01A0 R [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 ...

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ADE3XXX 2.25 DFT Block Register Name DFT_TEST_MODE DFT_MUX_OUT_MODE DFT_FLOP_OUT_MODE DFT_CLK_0UT_MODE DFT_CLK_1_MODE DFT_CLK_2_MODE DFT_OUT_DISAB_0 DFT_OUT_DISAB_1 DFT_OUT_DISAB_2 DFT_OUT_DISAB_3 DFT_OUT_DISAB_4 DFT_OUT_DISAB_5 DFT_OUT_DISAB_6 DFT_OUT_DISAB_7 DFT_STIM_CTRL DFT_STIM_EN_0 Table 31: DFT Registers (Sheet Addr Mode Bits Default 0x0F00 [7:4] R/W [3] 0x0 R/W ...

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I²C RAM Addresses Register Name DFT_STIM_EN_1 DFT_BIST_STATUS DFT_BIST_RESULT_0 DFT_BIST_RESULT_1 DFT_MFSR_DONE DFT_MFSR_SIG_0 DFT_MFSR_SIG_1 DFT_MFSR_SIG_2 DFT_MFSR_SIG_3 2.26 I²C RAM Addresses Name GAM_RED GAM_GREEN GAM_BLUE 80/88 Table 31: DFT Registers (Sheet Addr Mode Bits 0x0F10 [7:6] R/W [5] R/W [4] ...

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ADE3XXX Name Start Addr. OSD_MB OSD_CS OSD_DRB SCL_COEFF SCL_LINE1 SCL_LINE2 SCL_LINE3 SCL_LINE4 Table 32: I²C RAM Addresses End Addr. 0x1700 0x175F OSD Color LUTs (32x24) 0x3000 0x5F3F OSD Character Map (1344x36x2 copies) 0x6000 0x647F OSD Screen Map (1152x8) 0x9000 0x98FF ...

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... Total Power Consumption (Analog Input, XGA@75Hz, 78.75MHz) TOTANA P Total Power Consumption (DVI Input, XGA@75Hz, 78.75MHz) TOTDVI P Total Power Consumption (Stand By Mode) STANDBY * Measured at nominal voltage supplies ** Measured at +10% voltage supplies 82/88 Parameter Table 33: ADE3100 Parameter ) AVDD18 ) DVDD18 ) IAVDD33 ) DVDD33 ) AVDD18 ) DVDD18 ...

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ADE3XXX Symbol Supply Current (Analog Input, XGA@75Hz, 135MHz) I 1.8V analog supply (I AVDD18 I 1.8V digital supply (I DVDD18 I 3.3V analog supply ( AVDD33 I 3.3V digital supply (I DVDD33 Supply Current (DVI Input, XGA@75Hz, 135MHz) I 1.8V ...

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Preliminary Thermal Data 3.4 Preliminary Thermal Data Symbol R Junction-to-Ambient Thermal Resistance thJA 3.5 Preliminary DC Specifications Test Conditions: DVDD33 = AVDD33 = 3.3V, DVDD18 = AVDD18 = XVDD18 = LVDD18 = 1.8V, and T = 25°C AMB 3.5.1 LVTTL ...

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ADE3XXX Symbol Parameter I Low Level Input current IL 3.6 Preliminary AC Specifications Symbol Parameter fDVI DVI input pixel frequency Vdvi_diff DVI differential input voltage Vdvi_icm DVI input common mode voltage Vdvi_vin DVI input voltage Idvi_leak DVI input leackage current ...

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Preliminary AC Specifications 4 Package Mechanical Data 156 157 Pin 1 Identification 208 1 Exact shape of each corner is optional Min 0.25 A2 3.20 B 0. 0.45 ...

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ADE3XXX 5 Revision History Version Date 0.1 22 Oct. 2002 First Issue 1.0 25 Nov 2002 Update of registers SMEAS_V_CTRL, 1.1 05 Feb 2003 Changed "Projection Display Engine" to "LCD Display Engine" on page 1. Changed header name “ADE3500X/3600X” to ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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