RTL8101L REALTEK, RTL8101L Datasheet
RTL8101L
Specifications of RTL8101L
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RTL8101L Summary of contents
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... PCI GPIO Status Register................................... 39 6.23 Context For Line-Out Descriptor........................ 39 6.24 Context For Line-In Descriptor .......................... 40 6.25 Descriptor Definition.......................................... 40 7. EEPROM (93C46) Contents................................ 42 7.1 Summary of RTL8101L’s EEPROM registers ..... 44 7.2 Summary of EEPROM Power Management registers........... 44 8. PCI Configuration Space Registers..................... 45 1 RTL8101L ...
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... Control Frame Reception........................... 56 10.12 LED Functions.................................................. 57 10.12.1 10/100 Mbps Link Monitor........................ 57 10.12.2 LED_RX.................................................... 57 10.12.3 LED_TX .................................................... 58 10.12.4 LED_TX+LED_RX................................... 58 11. Application Diagram............................................... 59 12. Electrical Characteristics........................................ 60 12.1 Temperature Limit Ratings:................................ 60 12.2 DC Characteristics:............................................. 60 12.3 AC Characteristics.............................................. 61 12.3.1 PCI Bus Operation Timing: ......................... 61 13. Dimensions ............................................................... 67 2 RTL8101L Rev.1.3 ...
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... Supports PCI target fast back-to-back transaction Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of RTL8101L's operational registers Supports PCI VPD (Vital Product Data) Supports ACPI, PCI power management Supports 25MHz crystal or 25MHz OSC as the internal clock source ...
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... RTL8101L is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The RTL8101L is highly integrated and requires no “glue” logic or external memory. The RTL8101L includes a PCI and Expansion Memory Share Interface (Realtek patent) for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management. ...
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... RXIN- 68 RXIN AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD 76 LED2 77 LED1 78 LED0 79 INTBB 80 INTAB 81 RTSB 82 GNTB 83 REQB 84 CBE3B 85 AD31 86 AD30 RTL8101L LQFP 87 AD29 88 GND 89 AD28 90 VDD 91 AD27 92 AD26 93 AD25 94 VDD25 95 VDD 96 AD24 97 PCICLK 98 IDSEL 99 GPIO1 100 GPIO0 1 AC_RSTB 2 GND 3 AC_SYNC 4 AC_DOUT 5 AC_DIN ...
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... As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. 82 Grant: This signal is asserted low to indicate to the RTL8101L that the central arbiter has granted ownership of the bus to the RTL8101L. This input is used when the RTL8101L is acting as a bus master. ...
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... RSTB must be held for a minimum of 120 ns. Pin Aux. Power Detect: This pin is used to notify the RTL8101L of the existence of Aux. power during initial power- PCI reset. This pin should be pulled high to the Aux. power via a resistor to detect the Aux. power. Doing so, will enable wakeup support from ACPI D3 cold or APM power-down ...
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... INTBB is used for function 1 device (Modem) to request an interrupt. 100 General Purpose I/O pins: Both can be programmed as input or output by bit0-1 of PCI GPIO Setup Register Description Description TX/RX TX/RX TX LINK100 LINK10/100 LINK10/100 LINK10 FULL RX Description Description RTL8101L 11 Link10/ ACT Link100/ ACT Full Rev.1.3 ...
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... RTL8101L Rev.1.3 ...
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... This pin must be pulled low by a resistor. Please refer to the application circuit for the correct value. 50 Clock run: This signal is used by the RTL8101L to request starting (or speeding up) the clock, CLK. CLKRUNB also indicates the clock status. For the RTL8101L, CLKRUNB is an open drain output as well as an input ...
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... Ethernet Controller Register Descriptions The RTL8101L provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W 000Ah R/W 000Bh ...
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... LSB of the mask byte of wakeup frame2 within offset LSBCRC3 LSB of the mask byte of wakeup frame3 within offset LSBCRC4 LSB of the mask byte of wakeup frame4 within offset LSBCRC5 LSB of the mask byte of wakeup frame5 within offset LSBCRC6 LSB of the mask byte of wakeup frame6 within offset RTL8101L Rev.1.3 ...
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... Transmit Status Register (TSD0-3) (Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8101L when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written not affected when software writes to these bits. These registers are only permitted to write by double-word access. After a software reset, all bits except OWN bit are reset to “ ...
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... Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8101L. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. ...
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... Receive Error Interrupt: 1 => Enable, 0 => Disable. ROK Receive OK Interrupt: 1 => Enable, 0 => Disable. Symbol SERR System Error: Set to 1 when the RTL8101L signals a system error on the PCI bus. TimeOut Time Out: Set to 1 when the TCTR register reaches to the value of the TimerInt register. ...
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... R/W 1 R/W 0 R/W 5.7 Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8101L. It controls such functions as Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R 30-26 ...
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... R/W 3 5.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8101L. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit R/W 31-28 - 27-24 R/W ...
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... The RTL8101L receives the error packet larger than 64-byte long when the RER8 bit is cleared. The power-on default is zero. If AER set, the RER will be set when the RTL8101L receives an error packet whose length is larger than 8 bytes. The RER8 is “ Don’t care “ ...
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... Rx buffer and the transfer has arrived at the end of the Rx buffer. When set to 1: The RTL8101L will keep moving the rest of the packet data into the memory immediately after the end of the Rx buffer, if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer ...
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... R 4-3 R 2-0 R 5.11 CONFIG 1: Configuration Register 1 2003-05-28 destination address reject. Symbol EEM1-0 Operating Mode: These 2 bits select the RTL8101L operating mode. EEM1 EEM0 Reserved EECS These bits reflect the state of EECS, EESK, EEDI & EEDO pins in auto-load or 93C46 programming mode. ...
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... Driver Load: Software may use this bit to make sure that the driver has been loaded. Writing Writing When the command register bits IOEN, MEMEN, and BMEN of the PCI configuration space are written, the RTL8101L will clear this bit automatically. LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register are used to program the LWAKE pin’ ...
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... Magic Magic Packet: This bit is valid when the PWEn bit of the CONFIG1 register is set. The RTL8101L will assert the PMEB signal to wakeup the operating system when the Magic Packet is received. Once the RTL8101L has been enabled for Magic Packet wakeup and ...
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... The wake-up frame 4 and 5, 6 and 7 are merged respectively into another 2 long wake-up frames. Please refer to 7.4 PCI Power Management functions for detailed description. Set to 0: The RTL8101L supports wake-up frames, each with masked bytes selected from offset 12 to 75. LWPME ...
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... Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8101L, RCR<ERTH[3:0]> won't be used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for the unfamiliar protocol ...
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... Link had been experienced fail state 1 = valid link established valid link established jabber condition detected jabber condition detected extended register capability basic register capability only. 25 RTL8101L Default/Attribute ...
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... Link Partner's binary encoded node selector. Currently only CSMA/CD <00001> is specified. 26 RTL8101L Default/Attribute The default value comes from ...
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... This 16-bit counter increments by 1 for each false carrier event cleared to zero by read command. Description/Usage Reserved 1 = set NWay to loopback mode. Reserved 1 = LED0 Pin indicates linkpulse 1 = Auto-neg experienced ability detect state 1 = Auto-neg experienced parallel detection fault state 1 = Auto-neg experienced link status check state Description/Usage 27 RTL8101L Default/Attribute - Default/Attribute h'[0000], R Default/Attribute ...
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... Default value. Disable Unicast Wakeup Frame with mask bytes of only DID field, which is its own physical address. The power-on default value of this bit is 0. FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM) 28 RTL8101L h'[0000], R Default/Attribute 0,WO - ...
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... R/W Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer supported by RTL8101L.) The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8101L Config5 register. 2003-05-28 1: Both Rx and Tx FIFO address pointers are updated in descending way from 1FFh and downwards. The initial FIFO address pointer is 1FFh. ...
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... PCI GPIO Setup Register (PCIGPIO) PCI GPIO Status Register (PCIGPIOSR) Symbol - Reserved LO_SDILO Assign the first descriptor to be run when LINE1-Out bus master starts. Symbol - Reserved LO_CDILO Indicates the current descriptor been running. Symbol - Reserved 30 RTL8101L Description Description Description Description Rev.1.3 ...
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... FIFO froze depends on the BU setting for descriptor. 0: resume DMA LO_Start LINE-Out DMA Start/Stop: 1: Start bus master transaction, and the first descriptor assigned in “Starting Descriptor Index”. 0: Stop bus master transaction 31 RTL8101L Description Description Rev.1.3 ...
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... LI_Curr_Last Current descriptor is the last descriptor. This bit will be auto cleared LI_LH The LINE-In bus master is not active or the last descriptor has finished transaction. This bit will be auto cleared by H/W when bus master is active. 32 RTL8101L Description Description Description Description Description Description ...
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... Descriptor Index”. 0: Stop bus master transaction Symbol LI_RSS The residual samples number should be read in system memory for current descriptor. (sample: a 16-bit word) Symbol LI_DBA LINE-In Descriptor Base Address [31:2]. LINE-In Descriptor Base Address [1:0]. Hardwired RTL8101L Description Description Description Rev.1.3 ...
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... Interrupt is not generated even GPI Interrupt Status is set. Symbol ACLINK_BZ AC-LINK busy: 1: AC-LINK is busy on a MC’97 register read/write transaction access is in progress It is set when controller is doing an AC-LINK read/write transaction auto cleared by hardware after the transaction has been finished or 34 RTL8101L Description Description Rev.1.3 ...
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... This bit reflects the state of bit 0 in Slot 12 of SDATA-IN. ACLINK_CB AC-LINK Command Bit: 1: Read mixer command 0: Write mixer command ACLINK_CIP AC-LINK Mixer Command Index Port Symbol ACLINK_DP Write: 16 bits mixer data written to MC’97. Read: 16 bits mixer read from MC’97. 35 RTL8101L Description Rev.1.3 ...
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... Symbol GPIOID MC97’s GPIO input data. Symbol SERR_IE SERR# Interrupt Enable: 1: Enable interrupt when RTL8101L signals SERR# on PCI bus 0: Disable SERR_IS SERR# Interrupt Status: 1: SERR# interrupt, RTL8101L signals SERR# on PCI bus SERR# interrupt. This controller will generate an SERR# interrupt when (SERR_IE=1) & ...
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... A low to high transaction on PCIGPIO0 will trigger the PCI PME state. - Reserved PCIGPIO1_IE PCIGPIO1 interrupt Enable (when PCIGPIO1 is used as input): 1: Enable 0: Disable A low to high transaction PCIGPIO1 will trigger the PCI interrupt. PCIGPIO0_IE PCIGPIO0 interrupt Enable (when PCIGPIO0 is used as input): 37 RTL8101L Description Rev.1.3 ...
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... R/W 0 R/W ❶ The PME# only be asserted when RTL8101L state. ❷ PCIGPIO[9:8] and PCIGPIO[1:0] are sticky bits like as PME_Status (PMCSR.15) and PME_EN (PMCSR.8) be power by Vaux. 2003-05-28 1: Enable 0: Disable A low to high transaction PCIGPIO0 will trigger the PCI interrupt. - Reserved PCIGPIO1_PC PCIGPIO1 Primitiveness Control: ❷ ...
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... Drive PCIGPIO1 low (output). PCIGPIO0_IOS PCIGPIO0 Input/Output Status: ❷ 1: PCIGPIO0 is driven high by external device (input). / Drive PCIGPIO0 high (output). 0: PCIGPIO0 is driven low by external device (input). / Drive PCIGPIO0 low (output). Symbol EEM1-0 Operating Mode: These 2 bits select the RTL8101L operating mode. EEM1 EEM0 Reserved EECS These bits reflect the state of EECS, EESK, EEDI & ...
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... DMA Address for Line-In Descriptor 01h Buffer Size for Line-In Descriptor 01h DMA Address for Line-In Descriptor 1Eh Buffer Size for Line-In Descriptor 1Eh DMA Address for Line-In Descriptor 1Fh Buffer Size for Line-In Descriptor 1Fh DMA Start Address [31: RTL8101L Description : : Description : : 2 1 Buffer Length ...
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... BU bit is only effective for LINE1-Out master) Buffer Length [14:0]: The size of data buffer is in number of 16-bit sample. So the maximum number of samples is 32767. A value of 0 means there is no sample transferred into this buffer. To achieve an efficient PCI transaction, the buffer length must be an even number. 2003-05-28 41 RTL8101L Rev.1.3 ...
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... The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below by bytes for convenience. After the valid duration of the RSTB pin or auto-load command in the 9346CR, the RTL8101L performs a series of EEPROM read operations from the 93C46 addresses 00H to 31H. ...
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... Device ID of MC’97 Controller. Sub-Vendor ID of MC’97 Controller. Sub-Device ID of MC’97 Controller. Reserved. Do not change this field without Realtek approval. PHY Parameter 1-T for RTL8101L. Operational registers of the RTL8101L are from 78h to 7Bh. Reserved. Do not change this field without Realtek approval. Reserved. ...
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... Summary of RTL8101L’s EEPROM registers Offset Name Type 00h-05h IDR0 – IDR5 R/W* 51h CONFIG0 52h CONFIG1 58h MSRBMCR 63H 59h CONFIG3 5Ah CONFIG4 R/W * RxFIFO ** 78h-7Bh PHY1_PARM R/W ** 7Ch-7Fh TW1_PARM R/W TW2_PARM ** 80h PHY2_PARM R/W D8h CONFIG5 R/W * The registers marked with type = 'W *' can be written only if bits EEM1=EEM0=1. ...
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... MEM11 MEM10 MEM20 MEM19 MEM18 MEM28 MEM27 MEM26 SVID4 SVID3 SVID2 SVID12 SVID11 SVID10 SMID4 SMID3 SMID2 SMID12 SMID11 SMID10 ILR4 ILR3 ILR2 RTL8101L Bit1 Bit0 MEMEN IOEN MEMEN IOEN FBTBEN SERREN - SERREN 0 0 DST0 DPD - DPD LTR1 LTR0 LTR1 LTR0 ...
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... PERRSP Parity Error Response: When set to 1, the RTL8101L will assert the PERRB pin on the detection of a data parity error when acting as the target, and will sample the PERRB pin as the master. When set to 0, any detected parity error is ignored and the RTL8101L continues normal operation. ...
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... Special Cycle Enable: Read as 0, write operation has no effect. The RTL8101L ignores all special cycle operation. 2 BMEN Bus Master Enable: When set to 1, the RTL8101L is capable of acting as a bus master. When set prohibited from acting as a PCI bus master. For the normal operation, this bit must be set by the system BIOS. 1 MEMEN Memory Space Access: When set to 1, the RTL8101L responds to memory space accesses ...
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... Reserved 0 IOIN IO Space Indicator: Read only. Set the RTL8101L to indicate that it is capable of being mapped into IO space. MEMAR: This register specifies the base memory address for memory accesses to the RTL8101L operational registers. This register must be initialized prior to accessing any RTL8101L's register with memory access. ...
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... PME#. Write a “0” has no effect. Note that bit 15 is independent of bit 8. —Write “01” and “10” to bit 1,0 has no effect to RTL8101L. RTL8101L terminate the cycle normally and discard the data (bit 1,0 only). ...
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... BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR2 Ptr7 Ptr6 Ptr5 RESERVED(ALL Bit4 Bit3 Bit2 BMEN MEMEN NewCap RTABT STABT - LTR4 LTR3 LTP2 BMAR1 8 BMAR2 6 Ptr4 Ptr3 Ptr2 RTL8101L Bit1 Bit0 IOEN SERREN DPD LTR1 LTR0 BROMEN - BROMEN BMAR16 7 BMAR24 5 Ptr1 Ptr0 0 0 Rev.1.3 ...
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... PMC 76 not recommended to set the D0_support_PME bit to “1”. Link Wakeup occurs only when the following conditions are met: ♦ The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is in isolation state, or the PME# can be asserted in current power state. 2003-05-28 ...
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... Wakeup Frame pairs, are frames 4 and 5, and frames 6 and 7. The CRC5, CRC7, LSBCRC5, and LSBCRC7 have no meaning in this case and should be reset the RTL8101L is set to support long Wakeup Frame. In this case, the RTL8101L support 5 wakeup frames, that are 2 normal wakeup frames and 3 long wakeup frames. ...
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... Read VPD register: (read data from 93C46) Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8101L, the VPD data (all 4 bytes) has been transferred from 93C46 to the VPD data register. ...
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... Receive Logic Logic Interface Descrambler Scrambler Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M RTL8101L AC-Link Interface MII Interface RXD RXC 25M TXD TXC 25M TXO+ TXO - RXIN+ RXIN- Rev.1.3 ...
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... The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8101L is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8101L begins packet transmission ...
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... After detecting receive activity on the line, the RTL8101L starts to process the preamble bytes based on the mode of operation. While operating in 100Base-Tx mode, the RTL8101L expects the frame to start with the symbol pair JK in the first byte of the 8-byte preamble. The RTL8101L checks the CRC bytes and checks if the packet data ends with the TR symbol pair, if not, the RTL8101L reports an CRC error RSR. The RTL8101L reports a RSR< ...
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... Mbps Link Monitor The Link Monitor senses the link integrity station is down. 10.12.2 LED_RX In 10/100 Mbps mode, the LED function is like RTL8139C(L). 2003-05-28 Power On LED = Low No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8101L Rev.1.3 ...
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... LED_TX 10.12.4 LED_TX+LED_RX 2003-05-28 Power On LED = Low No Transmitting Packet Yes LED = High for (100 +- 10) ms LED = Low for ( Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8101L Rev.1.3 ...
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... Application Diagram RJ45 Magetics BootROM 2003-05-28 EEPROM LED AC-Link RTL8101L GPIO0-1 CS/OE Auxiliary Power INTAB PCI INTERFACE PCI Interface 59 RTL8101L Modem Codec INTBB Rev.1.3 ...
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... Average Operating Supply Current 2003-05-28 Minimum Maximum -55 +125 0 70 Conditions Minimum I OH= -8mA 0.9 * Vcc I OL= 8mA 0.5 * Vcc -0 GND -1.0 V OUT -10 GND I OUT= 0mA, 60 RTL8101L Units °C °C Maximum Units Vcc V 0.1 * Vcc V Vcc+0.5 V 0.3 * Vcc V 1 330 mA Rev.1.3 ...
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... AC Characteristics 12.3.1 PCI Bus Operation Timing: Target Read Target Write 2003-05-28 61 RTL8101L Rev.1.3 ...
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... Configuration Read Configuration Write 2003-05-28 62 RTL8101L Rev.1.3 ...
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... BUS Arbitration Memory Read 2003-05-28 63 RTL8101L Rev.1.3 ...
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... Memory Write Target Initiated Termination - Retry 2003-05-28 64 RTL8101L Rev.1.3 ...
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... Target Initiated Termination - Disconnect Target Initiated Termination - Abort 2003-05-28 65 RTL8101L Rev.1.3 ...
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... Master Initiated Termination – Abort Parity Operation - one example 2003-05-28 66 RTL8101L Rev.1.3 ...
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... Reference document: JEDEC MS-026 , BED. PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm APPROVE 3.5 ° 9 ° CHECK REALTEK SEMICONDUCTOR CORP. 67 and E do not include mold protrusion TITLE: 100LD LQFP ( 14x14x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION 1 PAGE OF DWG NO. LQ100 - P1 DATE RTL8101L Rev.1.3 ...
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... Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2003-05-28 68 RTL8101L Rev.1.3 ...