CY7C09159AV-9AC Cypress Semiconductor Corporation., CY7C09159AV-9AC Datasheet
CY7C09159AV-9AC
Specifications of CY7C09159AV-9AC
Related parts for CY7C09159AV-9AC
CY7C09159AV-9AC Summary of contents
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... Synchronous Dual Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09159AV) — 16K x 9 organization (CY7C09169AV) • Three Modes — Flow-Through — Pipelined — Burst • ...
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... Functional Description The CY7C09159AV and CY7C09169AV are high-speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is regis- tered for decreased cycle time ...
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... Max Access Time (Clock to Data, Pipelined) Typical Operating Current I CC Typical Standby Current for I (Both Ports TTL Level) SB1 Typical Standby Current for I (Both Ports CMOS Level) SB3 Note: 3. This pin is NC for CY7C09159AV. Document #: 38-06053 Rev. *B 100-Pin TQFP (Top View ...
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... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V Latch-Up Current ..................................................... >200 mA ° ° +150 C ° ° +125 C Operating Range Range +0.5V CC Commercial +0.5V CC [5] Industrial CY7C09159AV CY7C09169AV AND CE must be asserted MAX for x9 devices). 8 Ambient Temperature V CC ° ° +70 C 3.3V ± 300 mV ° ...
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... Ind. Test Conditions ° MHz 3. 250Ω TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) AND CE must be asserted to their active states ( CY7C09159AV CY7C09169AV CY7C09159AV CY7C09169AV -9 -12 Typ. Max. Min. Typ. Max. Unit 2.4 V 0.4 0.4 V 2.0 V 0.8 0.8 V µA 10 –10 10 135 230 115 ...
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... Data Output Hold After Clock HIGH DC t Clock HIGH to Output High Z CKHZ t Clock HIGH to Output Low Z CKLZ Port to Port Delays t Write Port Clock High to Read Data Delay CWDD t Clock to Clock Set-up Time CCS Document #: 38-06053 Rev. *B CY7C09159AV CY7C09169AV CY7C09159AV -9 -12 Min. Max. Min. Max ...
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... CL1 A A n CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09159AV CY7C09169AV n+3 t CKHZ Q n+1 n OHZ OLZ n n+1 n+2 t OHZ ...
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... CD2 HC CD2 SC CKHZ CKLZ [13, 14, 15, 16] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to. IH CY7C09159AV CY7C09169AV CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS Page (B1) [+] Feedback ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06053 Rev. *B [10, 17, 18, 19 n+1 n CD2 CKHZ Q n READ NO OPERATION [10, 17, 18, 19 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09159AV CY7C09169AV A A n+3 n CD2 CKLZ Q WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Page n+3 [+] Feedback ...
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... OUT OE Document #: 38-06053 Rev. *B [8, 10, 17, 18, 19 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [8, 10, 17, 18, 19 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09159AV CY7C09169AV n+3 n CD1 CD1 Q n CKLZ WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ READ Page [+] Feedback ...
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... Document #: 38-06053 Rev. *B [20] t SAD t SCN t CD2 n+1 DC COUNTER HOLD READ WITH COUNTER [20 n+1 n+2 READ WITH COUNTER . IH CY7C09159AV CY7C09169AV t HAD t HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+3 READ COUNTER HOLD WITH COUNTER Page ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06053 Rev. *B [21, 22 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD and equals the counter output when ADS = V IL CY7C09159AV CY7C09169AV n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page ...
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... HRST CNTRST t SD DATA DATA OUT COUNTER RESET Notes: 23 24. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06053 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09159AV CY7C09169AV n n READ READ ADDRESS n Page [+] Feedback ...
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... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09159AV CY7C09169AV Operation 9 [28] Deselected [28] Deselected Write [28] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...
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... Ordering Information 8K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code 9 CY7C09159AV-9AC CY7C09159AV-9AXC 12 CY7C09159AV-12AC CY7C09159AV-12AXC 16K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code 9 CY7C09169AV-9AC 12 CY7C09169AV-12AC CY7C09169AV-12AXC CY7C09169AV-12AI CY7C09169AV-12AXI Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 All products and company names mentioned in this document may be the trademarks of their respective holders ...
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... Document History Page Document Title: CY7C09159AV/CY7C09169AV 3.3V 8K/16K x 9 Synchronous Dual Port SRAM Document Number: 38-06053 Issue Orig. of REV. ECN NO. Date Change ** 110205 11/15/01 *A 122303 12/27/02 *B 393581 See ECN Document #: 38-06053 Rev. *B Description of Change SZV Change from Spec number: 38-00839 to 38-06053 ...