ISP1161 NXP Semiconductors, ISP1161 Datasheet
ISP1161
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ISP1161 Summary of contents
Page 1
... USB host only, a USB device only combined and configurable USB host and USB device capabilities. ISP1161 brings high flexibility to the systems that have it built-in. For example, a system that has ISP1161 built-in allows it not only to be connected USB hub that has a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard, USB mouse, among others ...
Page 2
... Fig 1. ISP1161 operating as a USB device. DSC Fig 2. ISP1161 operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161 operating as both USB host and device simultaneously. 9397 750 09567 Product data Full-speed USB single-chip host and device controller EMBEDDED SYSTEM P USB cable ...
Page 3
... Philips Semiconductors 2. Features Complies with Universal Serial Bus Specification Rev 2.0 The Host Controller portion of the ISP1161 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161 supports data transfer at full-speed (12 Mbit/s) Combines HC and single chip On-chip DC complies with most Device Class specifi ...
Page 4
... ISP1161BM LQFP64 plastic low profile quad flat package; 64 leads; body 7 9397 750 09567 Product data Full-speed USB single-chip host and device controller Rev. 02 — 13 December 2002 ISP1161 Version 10 1.4 mm SOT314-2 7 1.4 mm SOT414-1 © ...
Page 5
... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17 D15 ISP1161 HOST/ 28 DEVICE DACK2 27 AUTOMUX HOST BUS DACK1 34 INTERFACE EOT 26 DREQ2 25 DREQ1 30 INT2 DEVICE BUS ...
Page 6
... MEMORY MANAGEMENT UNIT REGISTER ACCESS Host controller sub-blocks INTEGRATED DMA HANDLER RAM MEMORY P HANDLER MANAGEMENT UNIT EP HANDLER Device controller sub-blocks Rev. 02 — 13 December 2002 ISP1161 USB Interface USB STATE clock recovery PHILIPS FRAME SIE MANAGE- MENT PDT_LIST USB PROCESS TRANSCEIVER MGT930 3 ...
Page 7
... TTL input; three-state output 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 13 December 2002 ISP1161 48 D_DM 47 H_PSW2 46 H_PSW1 DGND 45 44 XTAL2 ...
Page 8
... V or left unconnected. In all cases, decouple this pin to DGND HC’s DMA request output 1 (programmable polarity); signals to the DMA controller that the ISP1161 wants to start a DMA transfer; see 26 O DC’s DMA request output 2 (programmable polarity); signals to the DMA controller that the ISP1161 wants to start a DMA transfer ...
Page 9
... NDP field in the HcRhDescriptorA register; both ports will always be enabled 34 I DMA master device to inform ISP1161 of end of DMA transfer; active level is programmable; see 35 - digital ground 36 O DC’s ‘suspend’ state indicator output; active HIGH ...
Page 10
... I/O bit 0 of bidirectional data; slew-rate controlled; TTL input; three-state output 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 13 December 2002 ISP1161 , V and V . reg(3.3) hold1 hold2 pin is CC pin CC Table 3 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 11
... HC and the DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161’s DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V connection is established through a command sent by the external or system microprocessor. This allows the system microprocessor to complete its initialization sequence before deciding to establish connection with the USB ...
Page 12
... DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161 the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
Page 13
... CS and the address lines A1 and A0. However, the direction of the access of the I/O ports is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from ISP1161’s data port. When WR is LOW, the microprocessor writes a command to the command port, or writes data to the data port ...
Page 14
... ISP1161’s register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161 to the next register to be accessed. A command is 8 bits long microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte fi ...
Page 15
... Philips Semiconductors Fig 12. 16-bit register access cycle. Most of ISP1161’s internal control registers are 16 bits wide. Some of the internal control registers, however, have 32-bit width. internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor should fi ...
Page 16
... FIFO buffer RAM by DMA mode The DMA interface between a microprocessor and ISP1161 is shown in When doing a DMA transfer, at the beginning of every burst the ISP1161 outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC and DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA ...
Page 17
... Philips Semiconductors acknowledge to ISP1161 via the DACK pin (DACK1 for HC and DACK2 for DC), and at the same time, do the DMA transfer through the data bus. In the DMA mode, the microprocessor must still issue signal to ISP1161’ pin. ISP1161 will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer ...
Page 18
... EOT N = 1/2 byte count of transfer data number of cycles or burst. Fig 18. DMA transfer in burst mode. 8.6 Interrupts ISP1161 has separate interrupt request pins for USB HC (INT1) and USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 Mode 1 ...
Page 19
... HcInterruptEnable register is also logic 1, 9397 750 09567 Product data Full-speed USB single-chip host and device controller HcµPInterrupt register OR OR INT1 LATCH Rev. 02 — 13 December 2002 ISP1161 Figure 20. HcµPInterruptEnable register HcHardwareConfiguration register LE InterruptPinEnable MGT945 Figure © ...
Page 20
... The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1161 Host Controller, the following procedure should be followed: 1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is set to logic 1. ...
Page 21
... DcInterrupt register. SETUP and OUT token interrupts are generated after ISP1161’s DC has acknowledged the associated data packet. In bulk transfer mode, ISP1161’s DC will issue interrupts for every ACK received for an OUT token or transmitted for an IN token ...
Page 22
... SOF asserted.) Figure 22): When an interrupt event occurs (for example, SOF interrupt) Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted Figure 22): If the firmware sets bit INTENA to logic 0, pin INT2 will still Rev. 02 — 13 December 2002 ISP1161 LATCH INT2 LE INTENA 22 ...
Page 23
... Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt commands. For more information on interrupt control, see Section 9397 750 09567 Product data Full-speed USB single-chip host and device controller 13.3.6. Rev. 02 — 13 December 2002 ISP1161 Section 13.1.3, Section 13.1.5 and © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 24
... It is caused by the HostControllerReset field of the HcCommandStatus register (02H - read, 82H - write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161 USB HC is under the USB Operational State. Therefore, the HCD must set HostControllerFunctionalState field of the HcControl register before generating USB traffic. ...
Page 25
... Prepare PTD data in P system RAM The communication channel between the HCD and ISP1161’s USB the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets. ...
Page 26
... The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161’s HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
Page 27
... Product data Full-speed USB single-chip host and device controller 5 4 ActualBytes[7:0] Active MaxPacketSize[7:0] TotalBytes[7:0] reserved FunctionAddress[6:0] reserved Rev. 02 — 13 December 2002 ISP1161 Toggle ActualBytes[9:8] Last Speed MaxPacketSize[9:8] DirectionPID[1:0] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 0 ...
Page 28
... BufferUnderrun During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 29
... This will use the internal FIFO buffer RAM for only ATL transfers. 9397 750 09567 Product data Full-speed USB single-chip host and device controller …continued Figure 26 (ITL buffer size) 1000H (that is 4 kbytes) Rev. 02 — 13 December 2002 ISP1161 shows the partitions of the © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 30
... The data transfer can be done via PIO mode or DMA mode. The data transfer rate can Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. For the multi-cycle burst mode cycles per burst are supported for ISP1161. 9397 750 09567 Product data ...
Page 31
... Remark: The PTD is defined for both ATL and ITL type data transfer. For ITL, the PTD data should be put into ITL buffer RAM, the ISP1161 takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 27. Buffer RAM data organization. ...
Page 32
... Operation and C program example Figure 29 mode. ISP1161 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H - read, C0H - write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H - read, C1H - write) ...
Page 33
... ATLBufferPort (16-bit width) T 000H 000H 001H 001H 3FFH 7FFH ITL1 buffer RAM (8-bit width) shows the results after running this program. Rev. 02 — 13 December 2002 ISP1161 EOT internal EOT toggle SOF BufferStatus Pointer automatically increments by 2 ATL buffer RAM ...
Page 34
... Command for ATL buffer write // write 80 (0x50) bytes of data into ATL buffer RAM for (i=0;i<wCount;i++) 9397 750 09567 Product data Full-speed USB single-chip host and device controller Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 35
... HC initialized and under Operational state yes Rev. 02 — 13 December 2002 ISP1161 Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 36
... SOF comes (the beginning of the fourth frame) the ITL0BufferDone bit will be 9397 750 09567 Product data Full-speed USB single-chip host and device controller 5). The active bit is cleared only if all data of the Philips Transfer Descriptor Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 37
... CPU is fast enough to read back and download a AT interrupt (frame N 1) (frame N 2) read AT(N) write AT(N 1) Figure 31), the microprocessor is still busy transferring the AT data (frame N 1) (frame N 2) Rev. 02 — 13 December 2002 ISP1161 (frame N 3) MGT954 (frame N 3) MGT955 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 38
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built in ISP1161 for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15Kresistorsel) of the HcHardwareConfi ...
Page 39
... Product data Full-speed USB single-chip host and device controller ISP1161 D D bit 12 HcHardware Configuration internal MGT957 shows the ISP1161 downstream port power management scheme. regulator 3 detect H_OCn H_PSWn Rev. 02 — 13 December 2002 ISP1161 V BUS USB connector 22 ...
Page 40
... Full-speed USB single-chip host and device controller Figure 35, where H_DMn denotes either pin H_DM1 or H_DM2, to the source pole, and H_PSWn to the gate pole. We call the voltage drop ( V) results in a different overcurrent threshold. DSon Rev. 02 — 13 December 2002 ISP1161 is connected BUS of 150 m , the DSon © ...
Page 41
... V power supply instead of the 5 V power CC shows how to use an external OC detection circuit. Rev. 02 — 13 December 2002 ISP1161 HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE HcHardware Configuration ISP1161 MGT960 ’s CC © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 42
... The HC can be put into suspended state by setting the HcControl register (01H - read, 81H - write). See XOSC_6MHz XOSC (to DC PLL VOLTAGE REGULATOR DC_EnableClock Fig 37. ISP1161 suspend and resume clock scheme. 9397 750 09567 Product data Full-speed USB single-chip host and device controller 3 regulator detect H_OCn ...
Page 43
... The ISP1161 suspend and resume clock scheme is shown in Figure Remark: ISP1161 can be put into a fully suspended mode only after both the HC and the DC go into the suspended mode, when the crystal can be turned off and the internal regulator can be put into power-down mode. ...
Page 44
... HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational registers. This makes a provision that the OpenHCI HCD can be ported to ISP1161 easily. Reserved bits may be defined in future releases of this specification. To ensure inter operability, the HCD that does not use a reserved field must not assume that the reserved fi ...
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... Section 10.6.3 on page 74 16 Section 10.6.4 on page 75 16 Section 10.6.5 on page 75 16 Section 10.6.6 on page 76 16 Section 10.6.7 on page 77 Rev. 02 — 13 December 2002 ISP1161 Functionality HC Control and Status registers HC Frame Counter registers HC Root Hub registers HC DMA and Interrupt Control registers HC Miscellaneous registers HC Buffer RAM Control registers © ...
Page 46
... HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H reserved 00H R/W R/W R/W Rev. 02 — 13 December 2002 ISP1161 ...
Page 47
... USBRESUME state after detecting the resume signaling from a downstream port. The HC enters USBRESET after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved Rev. 02 — 13 December 2002 ISP1161 18 17 R/W R RWE ...
Page 48
... Full-speed USB single-chip host and device controller reserved 00H reserved reserved 00H R reserved R/W Rev. 02 — 13 December 2002 ISP1161 SOC[1: HCR © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 49
... Root Hub and no subsequent reset signaling should be asserted to its downstream ports. Section 10.1.5) and the MasterInterruptEnable bit reserved 00H R reserved 00H R reserved 00H R/W Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 50
... StartOfFrame: At the start of each frame, this bit is set by the HC and an SOF generated. - reserved SO SchedulingOverrun: This bit is set when USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. Rev. 02 — 13 December 2002 ISP1161 reserved © ...
Page 51
... RD 0 — ignore 1 — enable interrupt generation due to Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Rev. 02 — 13 December 2002 ISP1161 ...
Page 52
... RD 0 — ignore 1 — disable interrupt generation due to Resume Detect SF 0 — ignore 1 — disable interrupt generation due to Start of frame - reserved SO 0 — ignore 1 — disable interrupt generation due to Scheduling Overrun Rev. 02 — 13 December 2002 ISP1161 ...
Page 53
... FI[7: R/W HcFmInterval register: bit description Symbol Description FIT FrameIntervalToggle: The HCD toggles this bit whenever it loads a new value to FrameInterval. Rev. 02 — 13 December 2002 ISP1161 FI[13: R © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 54
... Reset sequence reserved reserved 00H FR[7: Rev. 02 — 13 December 2002 ISP1161 …continued FR[13: © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 55
... HcFmNumber register: bit description Symbol Description reserved FN[15:0] FrameNumber: This is incremented when HcFmRemaining is reloaded. It will be rolled over to 0H after FFFFH. When the USBOPERATIONAL state is entered, this will be incremented automatically. HC will set the StartofFrame in HcInterruptStatus. Rev. 02 — 13 December 2002 ISP1161 ...
Page 56
... LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining is equal or greater than this field. The value is calculated by the HCD, which considers transmission and set-up overhead. Rev. 02 — 13 December 2002 ISP1161 ...
Page 57
... POTPGT[7: reserved 00H R NOCP OCPM R/W R reserved Rev. 02 — 13 December 2002 ISP1161 NPS PSM R/W R NDP[1: © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 58
... NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub implementation-specific. The maximum number of ports supported is 2. Rev. 02 — 13 December 2002 ISP1161 2 ms. © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 59
... Full-speed USB single-chip host and device controller reserved N reserved N reserved N reserved N/A R Rev. 02 — 13 December 2002 ISP1161 PPCM[2: DR[2:0] IS R/W © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 60
... Device attached to Port 1 bit 2 — Device attached to Port reserved reserved reserved Rev. 02 — 13 December 2002 ISP1161 OCIC LPSC 0 0 R/W R © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 61
... On write—ClearGlobalPower: In global power mode (PowerSwitchingMode = 0), this bit is written to logic 1 to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. Rev. 02 — 13 December 2002 ISP1161 OCI LPS ...
Page 62
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes logic 1 to clear this bit. Writing logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 02 — 13 December 2002 ISP1161 ...
Page 63
... ClearPortPower: The HCD clears the PortPowerStatus bit by writing logic 1 to this bit. Writing logic 0 has no effect. Rev. 02 — 13 December 2002 ISP1161 …continued © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 64
... ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 02 — 13 December 2002 ISP1161 …continued © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 65
... PortEnableStatus bit. Writing logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is non removable (DeviceRemoveable[NDP]). Rev. 02 — 13 December 2002 ISP1161 …continued © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 66
... DACK1 is used with read and write signals. Power-up value. 1 — reserved EOTInputPolarity 0 — active LOW. Power-up value 1 — active HIGH DACKInputPolarity 0 — active LOW. Power-up value 1 — reserved Rev. 02 — 13 December 2002 ISP1161 AnalogOC reserved DACKMode Enable 0 0 ...
Page 67
... R DMA reserved Enable R/W R/W R/W HcDMAConfiguration register: bit description Symbol Description - reserved Rev. 02 — 13 December 2002 ISP1161 …continued DMACount ITL_ATL_ DMARead erSelect DataSelect WriteSelect R/W R/W R/W © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 68
... DREQ1 to be raised after bit DMA Enable is set ITL_ATL_ 0 — ITL buffer RAM selected for ITL data DataSelect 1 — ATL buffer RAM selected for ATL data DMARead 0 — read from ISP1161 HC’s FIFO buffer RAM WriteSelect 1 — write to ISP1161 HC’s FIFO buffer RAM ...
Page 69
... R OPR_Reg reserved Suspended R/W Hc PInterrupt register: bit description Symbol Description - reserved Rev. 02 — 13 December 2002 ISP1161 AllEOT ATLInt SOFITLInt Interrupt © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 70
... HC has handled must be read. To know the ITL buffer status, the HcBufferStatus register must first be read. This is for the microprocessor to get ISO data to or from the HC. For more information, see the 6th paragraph of Rev. 02 — 13 December 2002 ISP1161 …continued Section 9.5. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 71
... HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161 silicon chip. The high byte stands for the product name (here 61H stands for ISP1161). The low byte indicates the revision number of the product including engineering samples. ...
Page 72
... Full-speed USB single-chip host and device controller ChipID[15: ChipID[7: HcChipID register: bit description Symbol Description ChipID[15:0] ISP1161’s chip Scratch[15: R Scratch[7: R/W HcScratch register: bit description Symbol Description Scratch[15:0] Scratch register value ...
Page 73
... ITLBufferLength[15: R ITLBufferLength[7: R/W HcITLBufferLength register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 74
... ATLBuffer ITL1Buffer ITL0Buffer Done Done Done HcBufferStatus register: bit description Symbol Description - reserved Rev. 02 — 13 December 2002 ISP1161 1000H bytes. For example ATLBuffer ITL1Buffer ITL0Buffer Full ...
Page 75
... RdITL0BufferLength[7: HcReadBackITL0Length register: bit description Symbol Description RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by the microprocessor Rev. 02 — 13 December 2002 ISP1161 …continued © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 76
... RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by the microprocessor DataWord[15: R DataWord[7: R/W HcITLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ITL buffer RAM’s two data bytes. Rev. 02 — 13 December 2002 ISP1161 © ...
Page 77
... R DataWord[7: R/W HcATLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ATL buffer RAM’s two data bytes. Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 78
... DC data transfer operation The following session explains how the DC of ISP1161 handles an IN data transfer and an OUT data transfer. In Device mode, ISP1161 acts as a USB device data transfer means transfer from ISP1161 to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to ISP1161 ...
Page 79
... When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in). 9397 750 09567 Product data Full-speed USB single-chip host and device controller Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 80
... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1161 transmits); OUT: output from the USB host (ISP1161 receives). The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration register. 11.3.3 Endpoint FIFO size The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint ...
Page 81
... OUT (64-byte fixed) 1023 double-buffered 1023-byte isochronous endpoint 16 16-byte interrupt OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Rev. 02 — 13 December 2002 ISP1161 Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes ...
Page 82
... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161’s DC disables all endpoints and clears all DcEndpointConfiguration registers, except for the control endpoint which is fi ...
Page 83
... All signals connected to ISP1161’s DC must enter appropriate states to meet b. All input pins of ISP1161’s DC must have a CMOS logic 0 or logic 1 level the interrupt service routine the firmware must check the current status of the USB bus. When bit BUSTATUS in the DcInterrupt Register is logic 0, the USB bus has left ‘ ...
Page 84
... The D_SUSPEND output is active HIGH during ‘suspend’ state, making it suitable as a power switch control signal, e.g. for an external oscillator. Input pins of ISP1161’s DC are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application ...
Page 85
... DcInterruptEnable Register is set. 3. Maximum 15 ms after starting the wake-up sequence the ISP1161’s DC resumes its normal functionality case of a remote wake-up ISP1161’s DC drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output D_SUSPEND, the application restores itself and other system components to normal operating mode. ...
Page 86
... LOW level of input CS PWROFF selects powered-off mode during ‘suspend’ state all sending data AA37H unlocks the internal registers for writing after a ‘resume’ Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved 137 ...
Page 87
... I/O. ISP1161’s DC supports DMA transfer for all 14 configurable endpoints (see Only one endpoint at a time can be selected for DMA transfer. The DMA operation of ISP1161’s DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • ...
Page 88
... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1161’ 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
Page 89
... The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform ISP1161’s DC that it will start a DMA transfer. 7. ISP1161’s DC now places the word to be transferred on the data bus lines, because its RD signal was asserted by the 8237. ...
Page 90
... EOT DACK-only mode ISP1161’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. Fig 42. ISP1161’ ...
Page 91
... DMAEN = 0 87): Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred Rev. 02 — 13 December 2002 ISP1161 IN endpoint EOT is active transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer [1] [1] ...
Page 92
... Philips Semiconductors 13. DC commands and registers The functions and registers of ISP1161’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
Page 93
... DcEndpointStatusImage register endpoint 0 OUT DcEndpointStatusImage register endpoint 0 IN DcEndpointStatusImage register n endpoint Endpoint 0 IN and OUT DcErrorCode register endpoint 0 OUT DcErrorCode register endpoint 0 IN Rev. 02 — 13 December 2002 ISP1161 [1] Code (Hex) Transaction (00 bytes isochronous: N 1023 bytes; interrupt/bulk bytes ...
Page 94
... Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1161’s DC and to perform a device reset. 13.1.1 DcEndpointConfiguration (R/W: 30H–3FH/20H–2FH) This command is used to access the DcEndpointConfi ...
Page 95
... DcMode Register (R/W: B9H/B8H) This command is used to access the ISP1161’s DcMode register, which consists of 1 byte (bit allocation: see The DcMode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
Page 96
... Logic 1 enables SoftConnect (see ignored if EXTPUL = 1 in the DcHardwareConfiguration register (see Table 83). Bus reset value: unchanged. Table NOLAZY CLKRUN R/W R/W R/W Rev. 02 — 13 December 2002 ISP1161 2 1 DBGMOD reserved SOFTCT [1] [ R/W R/W R/W 8.6.3. Section 7.5). This bit is 83. A bus reset will not change any 10 ...
Page 97
... Selects the interrupt signalling mode on output pin INT2 (0 = level pulsed). In pulsed mode an interrupt produces an 166 ns pulse. See Section 8.6.3 unchanged. INTPOL Selects INT2 pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Rev. 02 — 13 December 2002 ISP1161 PWROFF INTLVL INTPOL 0 0 ...
Page 98
... Table 85 reserved R/W R/W R IEP12 IEP11 IEP10 R/W R/W R/W Rev. 02 — 13 December 2002 ISP1161 interrupt is cleared interrupt event 004aaa197 occurs Section 8.6. R/W R/W R IEP9 IEP8 IEP7 0 0 R/W R/W R/W © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 99
... DcDMAConfiguration Register (R/W: F1H/F0H) This command defines the DMA configuration of ISP1161’s DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of 2 bytes. The bit allocation is given in bit DMAEN (DMA disabled), all other bits remain unchanged. ...
Page 100
... Bus reset value: unchanged. 89. Writing to the register sets the number of bytes for a DMA transfer. Reading 13 12 DMACR[15: R/W R DMACR[7: R/W R/W Rev. 02 — 13 December 2002 ISP1161 Table Section 11.2. Section 13.1.6 for more details R/W R/W R ...
Page 101
... Table 90: Bit 13.1.8 Reset device (F6H) This command resets the ISP1161 DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 13.2 Data flow commands Data fl ...
Page 102
... Reading the DcEndpointStatus register will clear the interrupt bit set for the 13.2.3 EPFULL0 DATA_PID OVER WRITE Rev. 02 — 13 December 2002 ISP1161 command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) : Table 109 SETUPT ...
Page 103
... Logic 1 indicates that the buffer contains a SETUP packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 13 December 2002 ISP1161 Table 93). Section 11.3.6. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 103 of 137 ...
Page 104
... SETUP packet. SETUPT Logic 1 indicates that the buffer contains a SETUP packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 13 December 2002 ISP1161 Section 11.3. SETUPT CPUBUF 0 0 ...
Page 105
... PID encoding error; bits are not the inverse of bits PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data, or acknowledge SETUP token to a non-control endpoint token CRC error data CRC error Rev. 02 — 13 December 2002 ISP1161 Section 11.3. ERROR[3:0] ...
Page 106
... Unlock device (B0H) This command unlocks ISP1161’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
Page 107
... Scratch Information register reserved SOFRL[7: Symbol Description - reserved SOFRH[2:0] SOF frame number (upper byte) SOFRL[7:0] SOF frame number (lower byte) Rev. 02 — 13 December 2002 ISP1161 SFIR[12: R/W R/W R R/W R/W R/W Table 104 SOFRH[2: ...
Page 108
... R R Symbol Description CHIPIDH[7:0] chip ID code CHIPIDL[7:0] silicon version Table 109. Bit BUSTATUS is used to verify the current Section 29 28 reserved Rev. 02 — 13 December 2002 ISP1161 command code (B4H) ignored frame number ...
Page 109
... Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was detected on the USB bus. RESUME Logic 1 indicates that a ‘resume’ state was detected. RESET Logic 1 indicates that a bus reset condition was detected. Rev. 02 — 13 December 2002 ISP1161 EP9 EP8 EP7 ...
Page 110
... V hold1 V hold2 Fig 44. Using supply. 9397 750 09567 Product data Full-speed USB single-chip host and device controller Figure 44. ISP1161 has an internal DC/DC regulator to provide 3.3 V for its , V CC Figure 45. If, however, you have board space (routing area 1 USB upstream ...
Page 111
... Philips Semiconductors 15. Crystal oscillator and LazyClock The ISP1161 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure ISP1161 CLKOUT XTAL2 6 MHz XTAL1 Fig 46. Oscillator circuit with external crystal. ...
Page 112
... NOLAZY Fig 48. Oscillator and LazyClock logic. When ISP1161’s DC enters ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 kHz When resuming from ‘ ...
Page 113
... Product data Full-speed USB single-chip host and device controller Conditions V < > [1] I < Conditions with internal regulator internal regulator bypass [1] Rev. 02 — 13 December 2002 ISP1161 Min Max Unit 0.5 6.0 V 0.5 +4.6 V 0.5 +6 100 mA 2000 +2000 V 60 ...
Page 114
... DC is suspended HC is suspended DC is suspended HC is suspended = unless otherwise specified. GND amb Conditions [ [2] pin to GND Rev. 02 — 13 December 2002 ISP1161 Min Typ Max [1] 3.0 3.3 3 500 - 150 ...
Page 115
... C; unless otherwise specified. amb Conditions V V I(D ) I(D ) includes V range 1 3 GND L pin to GND enable internal resistors steady-state drive ) both H_D and H_D lines. Rev. 02 — 13 December 2002 ISP1161 Min Typ Max [1] 0 0 0.8 2 0.3 2.8 - 3.6 - ...
Page 116
... Conditions crystal oscillator running crystal oscillator stopped = pF; R amb L Conditions pF; 10 pF; 90 D.U. (full-speed mode). L Rev. 02 — 13 December 2002 ISP1161 Min Typ Max 160 - - [ 100 - 500 45 50 ...
Page 117
... WR data hold time WDH 9397 750 09567 Product data Full-speed USB single-chip host and device controller Figure 51 Conditions Min 5 8 300 110 143 110 136 Rev. 02 — 13 December 2002 ISP1161 Typ Max Unit - - ...
Page 118
... SHSL t RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 02 — 13 December 2002 ISP1161 t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid MGT969 Min Typ ...
Page 119
... Product data Full-speed USB single-chip host and device controller t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL (1) t SHWL t WHSH t WHDZ Rev. 02 — 13 December 2002 ISP1161 004aaa016 004aaa017 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 119 of 137 ...
Page 120
... Fig 54. HC single-cycle DMA timing. 9397 750 09567 Product data Full-speed USB single-chip host and device controller Conditions [ ALRL t SHAH t AHRH t RLDV t RHDZ data valid data valid t WSU t WHD Rev. 02 — 13 December 2002 ISP1161 Min Typ Max ...
Page 121
... Fig 55. HC burst mode DMA timing. 9397 750 09567 Product data Full-speed USB single-chip host and device controller Conditions Figure 55 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Rev. 02 — 13 December 2002 ISP1161 Min Typ Max 102 - - 22 ...
Page 122
... Full-speed USB single-chip host and device controller DREQ1 DACK1 EOT t RLIS 0 ns DREQ1 DACK1 EOT t RLIS 0 ns Conditions T cy(DREQ2) t ASRP (1) Rev. 02 — 13 December 2002 ISP1161 MGT972 MGT973 Min Typ Max - - 40 180 - - © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Unit ns ns MGT974 122 of 137 ...
Page 123
... DACK2 off APDZ 9397 750 09567 Product data Full-speed USB single-chip host and device controller Conditions Min - 25 180 - - t ASAP t ASRP t APRS t DVAP Conditions Min - 25 180 - - Rev. 02 — 13 December 2002 ISP1161 Typ Max Unit - APDZ 004aaa018 Typ Max Unit ...
Page 124
... Product data Full-speed USB single-chip host and device controller t ASAP t ASRP t DVAP Conditions EOT on; DACK on; RD/WR LOW t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Rev. 02 — 13 December 2002 ISP1161 t APRS t APDZ 004aaa018 Min Typ Max Unit ...
Page 125
... EOT on after RD LOW RLIS t input EOT on after WR LOW WLIS 9397 750 09567 Product data Full-speed USB single-chip host and device controller Conditions t RSIH t ILRP t IHIL Conditions EOT on; DACK on; RD/WR LOW Rev. 02 — 13 December 2002 ISP1161 Min Typ Max Unit ...
Page 126
... Programmable polarity: shown as active LOW. Fig 63. EOT timing in DC burst mode DMA. 9397 750 09567 Product data Full-speed USB single-chip host and device controller t ISRP t RLIS t WLIS (1) t EOT Rev. 02 — 13 December 2002 ISP1161 MGT978 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 126 of 137 ...
Page 127
... V hold1 hold2 H_WAKEUP H_SUSPEND D_WAKEUP D_SUSPEND NDP_SEL GL RESET D_VBUS CLKOUT CLKOUT XTAL2 6 MHz XTAL1 7 DGND AGND Rev. 02 — 13 December 2002 ISP1161 5 V (1) MOSFET (2 ) Vbus_DN2 Vbus_DN1 FB1 FB2 FB3 LED FB4 Vbus_UP FB5 V reg 22 1 ...
Page 128
... and will select the Data Port of the Device Controller – and will select the Command Port of the Device Controller • The CS line is used for chip selection of ISP1161 in a certain address range of the RISC system. This signal is active LOW. • ...
Page 129
... ISP1161. The software model for a Digital Still Camera (DSC) is used as the example for illustration (as shown in software are required to make full use of the features in ISP1161: the host stack and the device stack. The device stack provides API directly to the application task for device function ...
Page 130
... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 1.0 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 13 December 2002 ISP1161 SOT314 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.12 0.1 o 0.45 1.05 1.05 0 EUROPEAN ISSUE DATE PROJECTION 99-12-27 00-01-19 © ...
Page 131
... 2 scale (1) ( 0.20 7.1 7.1 9.15 9.15 0.4 1.0 0.09 6.9 6.9 8.85 8.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 13 December 2002 ISP1161 SOT414 detail X (1) ( 0.75 0.64 0.64 7 0.2 0.08 0.08 o 0.45 0.36 0.36 0 EUROPEAN ISSUE DATE PROJECTION 99-12-27 00-01-19 © ...
Page 132
... The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 09567 Product data Full-speed USB single-chip host and device controller Rev. 02 — 13 December 2002 ISP1161 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 132 of 137 ...
Page 133
... Product data Full-speed USB single-chip host and device controller methods [1] [4] , SO, SOJ Rev. 02 — 13 December 2002 ISP1161 Soldering method Wave Reflow not suitable suitable [3] not suitable suitable ...
Page 134
... DACK2 from the list item “Programmable.....pins DREQ2 and EOT”. 12.2: removed EOP from the second sentence of the third paragraph. Rev. 02 — 13 December 2002 ISP1161 36. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 134 of 137 ...
Page 135
... SHWL WLWH Figure 52. 120: 121: changed some minimum values. Also, changed t Figure 55, Figure 56 and Figure 57. 64: changed the resistor value on GL. Rev. 02 — 13 December 2002 ISP1161 . CC(susp 51 RLRH to t and added the last RL RLRH © Koninklijke Philips Electronics N.V. 2002. All rights reserved. ...
Page 136
... MIPS-based — trademark of MIPS Technologies, Inc. SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 02 — 13 December 2002 ISP1161 Fax: + 24825 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 136 of 137 ...
Page 137
... Static characteristics . . . . . . . . . . . . . . . . . . 114 19 Dynamic characteristics . . . . . . . . . . . . . . . . 116 19.1 Programmed I/O timing . . . . . . . . . . . . . . . . 117 19.2 DMA timing 120 20 Application information . . . . . . . . . . . . . . . . 127 20.1 Typical interface circuit . . . . . . . . . . . . . . . . . 127 20.2 Interfacing a ISP1161 with a SH7709 RISC processor 128 20.3 Typical software model . . . . . . . . . . . . . . . . . 129 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . 130 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 22.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 22.2 Refl ...