PTM1300AEBEA NXP Semiconductors, PTM1300AEBEA Datasheet
PTM1300AEBEA
Available stocks
Related parts for PTM1300AEBEA
PTM1300AEBEA Summary of contents
Page 1
TM-1300 Media Processor Product Specification Supersedes data of 1999 October 21 File under INTEGRATED CIRCUITS, TR1 INTEGRATED CIRCUITS 2000 May 30 ...
Page 2
Terms and Conditions TERMS AND CONDITIONS Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design ...
Page 3
Foreword The TriMedia TM-1300 is a higher speed, functionally enhanced version of the TM-1000 media processor. TM-1300 contains an ultra-high performance Very Long Instruction Word processor, as well as a complete intelli- gent video and audio input/output subsystem. The pro- ...
Page 4
TM1300 Data Book ii PRODUCT SPECIFICATION Philips Semiconductors ...
Page 5
Table of Contents Foreword 1 Pin List 1.1 TM1300 versus TM1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
TM1300 Data Book 2.4.1 Video Decompression ...
Page 7
Philips Semiconductors 3.5.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
TM1300 Data Book 5.3.9 Non-cacheable Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Philips Semiconductors 6.1.3 Power Down and Sleepless . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
TM1300 Data Book 7.14 EVO Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
Philips Semiconductors 9.5 Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 12
TM1300 Data Book 11.3 PCI Interface as an Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 13
Philips Semiconductors 11.7.16 DMA_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 14
TM1300 Data Book 13 System Boot 13.1 New in TM1300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 15
Philips Semiconductors 14.5.8 Implementation Overview: Vertical Scaling and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.5.8.1 Mirroring ...
Page 16
TM1300 Data Book 15.8 VLD DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 17
Philips Semiconductors 17.4.3 Interrupt and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 18
TM1300 Data Book 20.3.2 Arbitration Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 19
Philips Semiconductors allocr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 20
TM1300 Data Book fgeq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 21
Philips Semiconductors ifir8ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 22
TM1300 Data Book jmpf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 23
Philips Semiconductors st8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 24
TM1300 Data Book writedpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 25
Pin List by Muhammad Hafeez, Naeem Maan, Thorwald Rabeler, Luis Lucas, Gert Slavenburg 1.1 TM1300 VERSUS TM1100 The following summarizes pinout differences between TM1100 and TM1300: • TM1300 uses a BGA 27x27 package and is hence not physically pin compatible ...
Page 26
TM1300 Data Book 1.4 SIGNAL PIN LIST In the table below, a pin name ending in a ‘#’ designates an active-low signal (the active state of the signal is a low voltage level). All other signals have active-high polarity. BGA ...
Page 27
Philips Semiconductors BGA Pad Pin Name Mode Ball Type MM_DQ00 Y20 NORM3 I/O MM_DQ01 V18 MM_DQ02 W19 MM_DQ03 W20 MM_DQ04 U18 MM_DQ05 V19 MM_DQ06 V20 MM_DQ07 T18 MM_DQ08 W18 MM_DQ09 V17 MM_DQ10 Y18 MM_DQ11 W17 MM_DQ12 Y17 MM_DQ13 W16 MM_DQ14 ...
Page 28
TM1300 Data Book BGA Pad Pin Name Mode Ball Type PCI_AD00 T1 PCI I/O PCI_AD01 R3 PCI_AD02 R2 PCI_AD03 R1 PCI_AD04 P2 PCI_AD05 P1 PCI_AD06 N2 PCI_AD07 N1 PCI_AD08 M2 PCI_AD09 M1 PCI_AD10 L2 PCI_AD11 L1 PCI_AD12 K1 PCI_AD13 K2 ...
Page 29
Philips Semiconductors BGA Pad Pin Name Mode Ball Type PCI_INTA# C9 PCIOD I/OD PCI_INTB# A8 PCI I/O/OD PCI_INTC# B8 PCIOD I/OD PCI_INTD# A7 PCIOD I/OD JTAG Interface (debug access port and 1149.1 boundary scan port) JTAG_TDI F20 WEAK5 JTAG_TDO F18 ...
Page 30
TM1300 Data Book BGA Pad Pin Name Mode Ball Type VO_IO2 H20 WEAK5 I/O VO_CLK J19 STRG5 I/O Audio In (always acts as receiver, but can be master or slave for A/D timing) AI_OSCLK B15 STRG3 OUT AI_SCK A16 STRG5 ...
Page 31
Philips Semiconductors BGA Pad Pin Name Mode Ball Type Audio Out (always acts as sender, but can be master or slave for D/A timing) AO_OSCLK B14 STRG3 OUT AO_SCK A14 STRG5 I/O AO_SD1 B13 WEAK5 OUT AO_SD2 A13 WEAK5 OUT ...
Page 32
TM1300 Data Book 1.5 POWER PIN LIST VSS (ground C16 H9 L10 D4 H10 L11 D5 H11 L12 D16 H12 L13 D17 H13 M10 E17 J10 M11 E18 J11 M12 T3 ...
Page 33
Philips Semiconductors 1.6 PIN REFERENCE VOLTAGE With the exception of Open Drain mode outputs, outputs always drive to a level determined by the 3.3-V I/O voltage. VREF_PERIPH and VREF_PCI purely determine input voltage clamping, not input signal thresholds or output ...
Page 34
... ORDERING INFORMATION To order 143-MHz v1.2 TM-1300 parts, refer to part number ‘PTM1300AEBEA’ product code 9352 6691 7557. To order 166-MHz v1.2 TM-1300 parts, refer to part number ‘PTM1300FBEA’ product code 9352 6687 1557. SOT number is 553AA1. 1-10 PRODUCT SPECIFICATION ø2.0 0.10 R 0.625X3 ø17mm (Heat Slug) 0 ...
Page 35
Philips Semiconductors 1.9 PARAMETRIC CHARACTERISTICS 1.9.1 Operating Range and Thermal Characteristics Functional operation, long-term reliability and AC/DC characteristics are guaranteed for the operating conditions below. Symbol V Core supply voltage DD V I/O supply voltage CC T Operating case temperature ...
Page 36
TM1300 Data Book 1.9.4.1 TM-1300 and DSPCPU Core Current and Power Consumption Details TM1300-100:100 Symbol Current/Notes Pwd TM-1300 I 170 DD (note Total Power Dissipation 0 DSPCPU Only DSPCPU Only CC ...
Page 37
Philips Semiconductors 1.9.4.2 TM-1300 Peripheral Current Consumption Details TM1300-100:100 Symbol Current/Notes Pwd running raw mode MHz I , running raw mode running raw mode DD 81 MHz I , running ...
Page 38
TM1300 Data Book 1.9.4.3 STRG3, STRG5 type I/O circuit Symbol Parameter V Output HIGH voltage I OH OUT V Output LOW voltage I OL OUT Z Output AC impedance HIGH level output state OH Z Output AC impedance LOW level ...
Page 39
Philips Semiconductors 1.9.4.7 SDRAM interface timing Symbol f MM_CLK frequency SDRAM T Skew between MM_CLK0, CLK1 CS T Propagation delay of data, address, control PD T Output hold time of data, address and control OH T Input data setup time ...
Page 40
TM1300 Data Book 1.9.4.9 JTAG I/O timing Symbol f JTAG clock frequency JTAG-CLK T JTAG_TCK to JTAG_TDO valid delay clk-TDO T Input setup time to JTAG_TCK su-TCK T Input hold time from JTAG_TCK h-TCK Notes: 1. See the timing measurement ...
Page 41
Philips Semiconductors 1.9.4.13 AudioIn I/O timing Symbol f Audio In AI_SCK clock frequency AI-SCK T Input setup time to AI_SCK su-SCK T Input hold time from AI_SCK h-SCK T AI_SCK to AI_WS SCK-WS Notes: 1. See the timing measurement conditions ...
Page 42
TM1300 Data Book tm1300 pin 2” true length Output 50-ohm Buffer Figure 1-2. NORM3 test load circuit tm1300 pin 2” true length Output 50-ohm Buffer Figure 1-3. WEAK5 test load circuit CLK V_test T_fval Output Delay T_rval Output Delay Tri-State ...
Page 43
Philips Semiconductors T T HIGH LOW SCL Figure 1-11 I/O Timing SCL T TBUF SDA 2 Figure 1-12 I/O Timing SCL T su_STA SDA 2 Figure 1-13 I/O Timing SCL T ...
Page 44
TM1300 Data Book AO_SCK AO_SDx Figure 1-21. Audio Out I/O Timing AO_SCK AO_WS Figure 1-22. Audio Out I/O Timing AO_SCK T su_SCK valid AO_WS Figure 1-23. Audio Out I/O Timing 1-20 PRODUCT SPECIFICATION SSI_CLK T SCK_DV valid SSI I/O Figure ...
Page 45
Overview 2.1 INTRODUCTION TM1300 is a successor to the TM1100 and TM1000 me- dia processors. For those familiar with the TM1100, the new features specific to the TM1300 are summarized in Section 2.6. For those familiar with the TM1000, new ...
Page 46
TM1300 Data Book Software compatibility between current and future Trime- dia processor family members is at the source-code and library API level; binary compatibility between family members is not guaranteed. Defining software compatibility at the source-code level gives Philips the ...
Page 47
Philips Semiconductors 2.4 BRIEF EXAMPLES OF OPERATION The key to understanding TM1300 operation is observ- ing that the DSPCPU and peripherals are time-shared and that communication between units is through SDRAM memory. The DSPCPU switches from one task to the ...
Page 48
TM1300 Data Book Although the processor core runs a real-time operating system to coordinate all activities in the TM1300 system, the core is not intended for true general-purpose comput- er use. For example, the TM1300 processor core does not implement ...
Page 49
Philips Semiconductors PC Screen FrameMaker 5 File Edit Format View IMAGE 1 Calendar File Edit Image 2 Image 1 Figure 2-3. ICP - Windows on the PC screen and data structures in SDRAM for two live video windows. Figure 2-3 ...
Page 50
TM1300 Data Book As with the video units, the audio-in and audio-out units buffer incoming and outgoing audio data in SDRAM. The audio-in unit buffers samples in either 8- or 16-bit format, mono or stereo. The audio-out unit transfers 16- ...
Page 51
DSPCPU Architecture 3.1 BASIC ARCHITECTURE CONCEPTS This section documents the system programmer or ‘bare-machine’ view of the TM1300 CPU (or DSPCPU). 3.1.1 New in TM1300 Default reset value of PCSW register is 0x800. This new reset value allows Audio Out ...
Page 52
TM1300 Data Book 3.1.3 Basic DSPCPU Execution Model The DSPCPU issues one ‘long instruction’ every clock cycle. Each instruction consists of several operations (five operations for the TM1300 microprocessor). Each operation is comparable to a RISC machine instruction, except that ...
Page 53
Philips Semiconductors Table 3-2. PCSW FP exception flag definitions Flag Function INV Standard IEEE invalid flag OVF Standard IEEE overflow flag UNF Standard IEEE underflow flag INX Standard IEEE inexact flag DBZ Standard IEEE divide-by-zero flag OFZ ‘Output flushed to ...
Page 54
TM1300 Data Book 3.1.8 Integer Representation The architecture supports the notion of 'unsigned inte- gers' and 'signed integers.' Signed integers use the stan- dard two’s-complement representation. Arithmetic on integers does not generate traps result is not representable, the ...
Page 55
Philips Semiconductors 3.2 INSTRUCTION SET OVERVIEW 3.2.1 Guarding (Conditional Execution) In the TM1300 architecture, all operations can be option- ally 'guarded'. A guarded operation executes conditional- ly, depending on the value in the ‘guard' register. For ex- ample, a guarded ...
Page 56
TM1300 Data Book 3.2.3 Compute Operations Compute operations are register-to-register operations. The specified operation is performed on one or two source registers and the result is written to the destina- tion register. Immediate Operations. Immediate operations load an immediate constant ...
Page 57
Philips Semiconductors • functional units should be ‘recovered’ from any prior operation issues Writeback constraint: • No more than 5 results should be simultaneously written to the register file at any point in time (write- back occurs ‘latency’ cycles after ...
Page 58
TM1300 Data Book for PC-hosted TM1300 boards; its final location is deter- mined by the boot EEPROM for standalone systems. See Chapter 13, “System Boot” for more information. Figure 3-5 gives a detailed overview of the MMIO mem- ory map ...
Page 59
Philips Semiconductors The instruction scheduler uses interruptible jumps exclu- sively for inter-decision tree jumps. Hence, within a deci- sion tree, no special-event processing can be initiated tree-to-tree jump is taken, special-event processing is allowed. Since the only registers ...
Page 60
TM1300 Data Book Programmer’s note: See the Philips TriMedia Cookbook (Book 2 of TriMedia SDE documentation) for information on writing interrupt handlers. 3.5.3.2 Interrupt modes DSPCPU interrupt sources can be programmed to oper- ate in either level-sensitive or edge-triggered mode. ...
Page 61
Philips Semiconductors device events lead to the request of an interrupt. In addi- tion, the PCSW.IEN flag determines whether the DSPCPU is willing to handle regular interrupts. Non maskable interrupts ignore the state of this flag. All three mechanisms are ...
Page 62
TM1300 Data Book MMIO_BASE offset: 0x10 3038 INT_CTL (r/w) Figure 3-9. Host interrupt control register Table 3-10. Interrupt source assignments SOURCE SRC MODE SOURCE DESCRIPTION NAME NUM PCI INTA 0 level PCI_INTA# pin signal PCI INTB 1 level PCI_INTB# pin ...
Page 63
Philips Semiconductors Timer base offset: 0 TMODULUS (r/w) 4 TVALUE (r/w) 8 TCTL (r/w) Figure 3-10. Timer register definitions. Table 3-11. Timer base MMIO address TIMER1 MMIO_BASE+0x10,0C00 TIMER2 MMIO_BASE+0x10,0C20 TIMER3 MMIO_BASE+0x10,0C40 SYSTIMER MMIO_BASE+0x10,0C60 Table 3-12. Timer source selections Source Source ...
Page 64
TM1300 Data Book MMIO_BASE offset: 0x10 1004 BINSTLOW (r/w) 0x10 1008 BINSTHIGH (r/w) Figure 3-12. Instruction-breakpoint address-range registers. MMIO_BASE offset: 0x10 1030 BDATAALOW (r/w) 0x10 1034 BDATAAHIGH (r/w) 0x10 1038 BDATAVAL (r/w) 0x10 103C BDATAMASK (r/w) Figure 3-13. Data-breakpoint address-range ...
Page 65
Philips Semiconductors Note: use a nonzero datamask or the result is undefined. When a successful comparison has taken place, a data breakpoint event is generated, which can be used as a clock input to a timer. After counting the set ...
Page 66
TM1300 Data Book 3-16 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 67
Custom Operations for Multimedia 4.1 CUSTOM OPERATIONS OVERVIEW Custom operations in the TM1300 DSPCPU architecture are specialized, high-function operations designed to dramatically improve performance in important multime- dia applications. When properly incorporated into appli- cation source code, custom operations enable ...
Page 68
TM1300 Data Book Table 4-1. Key Multimedia Custom Operations Listed by Function Type Function Custom Op DSP dspiabs Clipped signed 32-bit absolute absolute value value dspidualabs Dual clipped absolute values of signed 16-bit halfwords Shift dualasr dual-16 arithmetic shift right ...
Page 69
Philips Semiconductors Table 4-2. Key Multimedia Custom Operations Listed by Operand Size Op. Size Custom Op 8-bit quadumax Unsigned bytewise quad max quadumin Unsigned bytewise quad min dspuquadaddui Quad clipped add of unsigned/ signed bytes ifir8ii Signed sum of products ...
Page 70
TM1300 Data Book ld32d(0) r100 r10 ld32d(4) r100 r11 ld32d(8) r100 r12 ld32d(12) r100 r13 mergemsb r10 r11 r14 mergemsb r12 r13 r15 mergelsb r10 r11 r16 mergelsb r12 r13 r17 pack16msb r14 r15 pack16lsb r14 r15 pack16msb r16 r17 ...
Page 71
Philips Semiconductors void reconstruct (unsigned char *back, { int i, temp; for ( < 64 temp = ((back[i] + forward[ >> idct[i]; if (temp > 255) else if (temp ...
Page 72
TM1300 Data Book void reconstruct (unsigned char *back, { int i, temp; for ( < 64 temp = ((back[i+0] + forward[i+ >> idct[i+0]; if (temp > 255) temp = ...
Page 73
Philips Semiconductors void reconstruct (unsigned char *back, { int i, temp0, temp1, temp2, temp3; for ( < 64 temp0 = ((back[i+0] + forward[i+ >> 1); temp1 = ((back[i+1] + forward[i+1] + ...
Page 74
TM1300 Data Book void reconstruct (unsigned char *back, unsigned char *forward, unsigned char *destination) { int i; int *i_back = (int *) back; int *i_forward = (int *) forward; int *i_idct = (int *) idct; int *i_dest = (int *) ...
Page 75
Philips Semiconductors unsigned char A[16][16]; unsigned char B[16][16 for (row = 0; row < 16; row += 1) { for (col = 0; col < 16; col += 4) { cost0 = abs(A[row][col+0] – B[row][col+0]); cost1 = ...
Page 76
TM1300 Data Book unsigned int *IA = (unsigned int *) A; unsigned int *IB = (unsigned int *) B; for (row = 0; row < 16; row += 1) { int rowoffset = row * 4; for (col4 = 0; ...
Page 77
Cache Architecture 5.1 MEMORY SYSTEM OVERVIEW The high-performance video and audio throughput of TM1300 is implemented by its DSPCPU and autono- mous I/O and co-processing units, but the foundation of this processing is the TM1300 memory hierarchy. To get the ...
Page 78
TM1300 Data Book Table 5-2. Summary of memory system characteristics Unit Description Branch units Branch units execute branch operations three branch operations can be executed in parallel, but the program must guarantee that only one branch is taken. ...
Page 79
Philips Semiconductors 5.3 DATA CACHE The data cache serves only the DSPCPU and is con- trolled by two memory units that execute the load and store operations issued by the DSPCPU. The following sections describe the data cache and its ...
Page 80
TM1300 Data Book 5.3.3 Miss Processing Order When a miss occurs, the data cache fills the block con- taining the requested word from the critical word first. The CPU is stalled until the first word is transferred. The block is ...
Page 81
Philips Semiconductors MMIO_BASE offset: 0x10 0010 DC_LOCK_CTL (r/w) 0x10 0014 DC_LOCK_ADDR (r/w) 0x10 0018 DC_LOCK_SIZE (r/w) Figure 5-5. Formats of the registers in charge of data-cache locking. ‘1’. Setting DC_LOCK_ENABLE to ‘0’ causes no action except to allow the previously ...
Page 82
TM1300 Data Book 5.3.10 Special Data Cache Operations A program can exercise some control over the operation of the data cache by executing special operations. The special operations can cause the data cache to initiate the copyback or invalidation of ...
Page 83
Philips Semiconductors 5.3.10.3 Data cache allocation operation The data cache controller recognizes allocation opera- tions as shown in Table 5-9. The allocation operations al- locate a block and set the status of this block to valid. No data is fetched ...
Page 84
TM1300 Data Book 5.3.12 Operation Latency Load and store operations have an operation latency of three cycles, regardless of the size of the data transfer. 5.3.13 MMIO Register References Memory operations that reference MMIO registers are not cached, and the ...
Page 85
Philips Semiconductors Table 5-13. Instruction Address Field Partitioning Address Field Purpose Bits Offset 5..0 Byte offset into a set Set 11..6 Selects one of the sets in the cache (one the case of TM1300) Tag 31..12 Compared ...
Page 86
TM1300 Data Book Reading the LRU bits produces a 32-bit result with the format shown at the bottom of Figure nificant ten bits contain the state of the LRU bits when the ld32 was executed. See Section 5.6.7, “LRU Bit ...
Page 87
Philips Semiconductors 1. The stall signal is asserted to prevent activity in the DSPCPU and data cache. 2. The valid bits for all blocks in the instruction cache are reset the completion of the block invalidation scan, the ...
Page 88
TM1300 Data Book LRU bit 9 LRU bit 8 LRU bit 7 2_way[3] 2_way[2] 2_way[1] Figure 5-13. LRU bit definitions; 2_way[k] is the two-way LRU bit of pair div 2) for set element j. MMIO_BASE offset: 0x10 ...
Page 89
Philips Semiconductors for the TIMER CACHE1 source. Event2 selects the source for TIMER CACHE2. Table 5-14. Trackable cache-performance events Encoding Event 0 No event counted 1 Instruction-cache misses 2 Instruction-cache stall cycles (including data- cache stall cycles if both instruction-cache ...
Page 90
TM1300 Data Book 5-14 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 91
Video In 6.1 VIDEO IN OVERVIEW The Video In (VI) unit provides the following functions: • Digital video input from a digital camera or analog camera (using a video decoder). • High-bandwidth (81 MB/sec) raw input data channel. • Direct ...
Page 92
TM1300 Data Book Table 6-2. VI unit interface pins VI_CLK I/O-5 • If configured as input (power up default): a positive transition on this incoming video clock pin samples all other VI_DATA input signals below if VI_DVALID is HIGH. If ...
Page 93
Philips Semiconductors TM1300 1 VO_DATA[7:0] (STMSG) VO_IO1 (ENDMSG) VO_IO2 VO_CLK Figure 6-2. VI unit connected to an EVO unit of another TM1300. Analog video 1–2 S-VHS Y/C 1–4 CVBS Figure 6-3. VI unit connected to a video decoder. Analog video ...
Page 94
TM1300 Data Book 6.3 FULLRES CAPTURE MODE In fullres capture mode, the VI unit receives all three vid- eo components Y, U, and V, as well as synchronization information (SAV and EAV codes) on the VI_DATA[7:0] pins in CCIR656 format. ...
Page 95
Philips Semiconductors Figure 6-8. Format of CCIR656 SAV and EAV timing reference codes. Figure 6-9. VI capture parameters. VI_CTL.SC=1: ‘Interspersed sampling’ serves to gen- erate a sampling structure in memory where chromi- ...
Page 96
TM1300 Data Book • FIELD2: Indicates whether the field currently being received is a field1 or 2. This flag gets updated based on the F field of every received SAV code. Note that field1 is the ‘top’ field, i.e. the ...
Page 97
Philips Semiconductors Y_BASE_ADR Y_DELTA U_BASE_ADR U_DELTA Figure 6-10. VI YUV 4:2:2 planar memory format. U_DELTA and V_DELTA do affect the next horizontal re- trace. Hence, under normal circumstances, the DELTA variables should not be changed during capture. When capture is ...
Page 98
TM1300 Data Book MMIO_base offset: 0x10 1400 VI_STATUS (r) 0x10 1404 VI_CTL (r/w) Highway bandwidth error ACK 0x10 1408 VI_CLOCK (r/w) 0x10 140C VI_CAP_START (r/w) 0x10 1410 VI_CAP_SIZE (r/w) 0x10 1414 VI_Y_BASE_ADR (r/w) 0x10 1418 VI_U_BASE_ADR (r/w) 0x10 141C VI_V_BASE_ADR ...
Page 99
Philips Semiconductors YUV 4:2:2 CCIR656 input samples Halfres capture sample results Figure 6-13. Halfres co-sited sample capture. YUV 4:2:2 CCIR656 input samples Halfres capture sample results Figure 6-14. Halfres interspersed sample capture. 6.4 HALFRES CAPTURE MODE Halfres capture mode is ...
Page 100
TM1300 Data Book MMIO_BASE offset: 0x10 1400 VI_STATUS (r) 0x10 1404 VI_CTL (r/w) Highway bandwidth error ACK 0x10 1408 VI_CLOCK (r/w) 0x10 1414 VI_BASE1 (r/w) 0x10 1418 VI_BASE2 (r/w) 0x10 141C VI_SIZE (r/w) Figure 6-15. Raw and message passing modes ...
Page 101
Philips Semiconductors RESET ACK2 Figure 6-16. VI raw mode major states. VI_DATA[7:0] XX VI_DATA[8] Start of message VI_DATA[9] VI_CLK Figure 6-17. VI message passing signal example. 6.6 MESSAGE-PASSING MODE In this mode, VI receives 8-bit message data over the VI_DATA[7:0] ...
Page 102
TM1300 Data Book RESET No EOM raise OVERFLOW* See text in ( ACK2 No EOM raise OVERFLOW* See text in ( Figure 6-18. VI message passing mode major states. 6.7 HIGHWAY LATENCY AND HBE Refer to Chapter 20, “Arbiter,” for ...
Page 103
Philips Semiconductors In fullres mode, bandwidth requirements (in bytes) per video line with active image for VI is: • ceil(WIDTH*2/256 fullr ceil(X) function is the least integral value greater than or equal to X. ...
Page 104
TM1300 Data Book 6-14 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 105
Enhanced Video Out 7.1 ENHANCED VIDEO OUT SUMMARY The TM1300 Enhanced Video Out (EVO) improves on the design of the TM1000 Video Out (VO) unit while maintaining binary-compatibility. TM1300 EVO is fully backward compatible with TM1100, and has been ex- ...
Page 106
TM1300 Data Book 7.4.1 Detailed Feature Descriptions The EVO provides the following key functions. • Continuous digital video output of PAL or NTSC for- mat data according to CCIR 601. • Transmission of YUV 4:2:2 co-sited pixel data across a ...
Page 107
Philips Semiconductors TM1300 A VO_DATA[7:0] (STMSG) VO_IO1 (ENDMSG) VO_IO2 VO_CLK logic ‘1’ Figure 7-3. EVO unit connected to the VI unit of a second TM1300. Table 7-1. EVO unit interface pins Signal Name Type Description VO_DATA[7:0] OUT CCIR 656-style YUV ...
Page 108
TM1300 Data Book 90 MHz. The PLL is enabled and programmed as de- scribed in Section 7.18. DDS clock rate is set by the VO_CLOCK.FREQUENCY field according to the equation shown in VO_CLK frequency can be a divider or multiplier ...
Page 109
Philips Semiconductors Field Video Lines Vertical Blanking Sync 1/2 Line Interlace Offset Figure 7-9. Interlaced timing—NTSC analog sync. signals. Byte 0 VO_DATA[0: VO_CLK Figure 7-10. CCIR 656 pixel timing. SAV, EAV Codes E S ...
Page 110
TM1300 Data Book Table 7-2. SAV and EAV codes Code Binary Value Field SAV 1000 0000 1 EAV 1001 1101 1 SAV 1010 1011 1 EAV 1011 0110 1 SAV 1100 0111 2 EAV 1101 1010 2 SAV 1110 1100 ...
Page 111
Philips Semiconductors Counter and Image Pixel Counter define the visible im- age within the field. The geometry of the active video area is defined by the contents of several MMIO registers Figure 7-29. The VO_FRAME.FIELD_2_START field defines the start line ...
Page 112
TM1300 Data Book Field 1 Video Lines NTSC PAL Blanking Active Video Vertical Sync VO_IO2 Figure 7-14. EVO VO_IO2 timing in FIELD_SYNC mode. Image Data Blanking EAV SAV VO_IO1 Figure 7-15. EVO VO_IO1 timing ...
Page 113
Philips Semiconductors Image Data Line 525/625 EAV VO_IO2 Delay SLAVE_DLY in VO_CLK cycles Figure 7-16. Genlock mode. VO_DATA[7:0] XX VO_IO2 VO_IO1 VO_CLK Figure 7-17. Data-streaming valid data signals. VO_DATA[7: VO_IO1 Start of message VO_IO2 VO_CLK Figure 7-18. Message-passing ...
Page 114
TM1300 Data Book Figure 7-19. YUV 4:2:2 co-sited format. Figure 7-20. YUV 4:2:2 interspersed format. Figure 7-21. YUV 4:2:0 format. bles to generate the CCIR 656-compatible output data. The U and V tables have the same number of lines but ...
Page 115
Philips Semiconductors Input Pixels: YUV Output Pixels: YU’V’ Figure 7-24. YUV interspersed to co-sited conversion. U0,0; V0,0 Y0,0 Input Pixels: YUV 4:2:0 Y0,0; U0,0; V0,0 Output Pixels: YU’V’ 4:2:2 Figure 7-25. YUV 4:2:0 to YUV 4:2:2 co-sited conversion. 7.13 VIDEO ...
Page 116
TM1300 Data Book WIDTH pixels pix0 pix1 pix2 • Y_BASE_ADR Y_OFFSET WIDTH/2 pixels U_BASE_ADR pix0 pix2 • • • U_OFFSET Figure 7-22. Image storage in planar memory format for YUV 4:2:2. 7.13.3 YUV-2x Upscaling In the YUV-2 modes, the EVO ...
Page 117
Philips Semiconductors 1 Input Pixels Output Pixels: Y’ Y’=Y1 Y’=F(Y1,Y1,Y2,Y3) Figure 7-28. Mirroring pixels in 2x upscaling. 7.14 EVO OPERATING MODES EVO operating modes belong to two groups as follows: • Video-refresh modes • Data-transfer modes Data-transfer ...
Page 118
TM1300 Data Book The equations for the blending are illustrated below. if alpha[ then output[7:0] = overlay[7:0] else output[7:0] = (alpha[6:0] · overlay[7:0] + (alpha[6: · image[7:0]) >> 7 (or) output[7:0] = (alpha[6:0] · (overlay[7:0] – ...
Page 119
Philips Semiconductors MMIO_BASE offset: 0x10 1800 VO_STATUS (r) 0x10 1804 VO_CTL (r/w) RESET SLEEPLESS CLOCK_SELECT PLL_S 0x10 1808 VO_CLOCK (r/w) 0x10 180C VO_FRAME (r/w) 0x10 1810 VO_FIELD (r/w) 0x10 1814 VO_LINE (r/w) 0x10 1818 VO_IMAGE (r/w) 0x10 181C VO_YTHR (r/w) ...
Page 120
TM1300 Data Book Table 7-5. VO_STATUS — status register fields Field CUR_Y Current Y. Image line index of the current line in the current field being output by the EVO. CUR_Y reflects the current state of the Image Line Counter. ...
Page 121
Philips Semiconductors 525 Line / Blanking: Field 2 Overlap 4 Blanking: Field 1 20 Video Image: Field 1 264 Blanking: Field 1 Overlap 266 Blanking: Field 2 283 Video Image: Field 2 525 Figure 7-30. EVO frame ...
Page 122
TM1300 Data Book Table 7-6. VO_CTL register fields Field SYNC_MASTER Sync master. • When set, VO_IO1 and VO_IO2 are outputs. In video-refresh modes, the EVO generates horizontal and frame timing signals on VO_IO1 and VO_IO2 respectively. In message-passing mode and ...
Page 123
Philips Semiconductors Table 7-7. VO register fIelds Register Field VO_CLOCK FREQUENCY VO_FRAME FRAME_LENGTH FIELD_2_START FRAME_PRESET VO_FIELD F1_VIDEO_LINE F2_VIDEO_LINE F1_OLAP F2_OLAP VO_LINE FRAME_WIDTH VIDEO PIXEL START Pixel number in Frame Pixel Counter of starting pixel of active video area within the ...
Page 124
TM1300 Data Book Table 7-7. VO register fIelds Register Field VO_OLADD OL_BASE_ADDR SIZE2 VO_VUF U_OFFSET V_OFFSET VO_YOLF Y_OFFSET OL_OFFSET Table 7-8. If features are enabled, new TM1300 the func- tionality replaces TM1000 functions. The hardware reset value of EVO_CTL register ...
Page 125
Philips Semiconductors Table 7-8. EVO_CTL Register Fields Register Field EVO_CTL EVO_ENABLE When set to 1, new EVO features are enabled. When set to 0 (the hardware reset value), the EVO behaves exactly like a TM1000 VO unit. Default: 0. FULL_BLENDING ...
Page 126
TM1300 Data Book The VO_CLK signal is normally set as an output to drive the data transfer for all modes at a programmable rate. The VO_CLK signal can be an input or output, as con- trolled by the VO_CTL.CLKOUT bit. ...
Page 127
Philips Semiconductors Note: In this mode, SYNC_MASTER must be set to en- sure correct operation of VO_IO1 and VO_IO2 as out- puts. When each buffer has been transferred, the correspond- ing buffer-empty bit is set in the status register, and ...
Page 128
TM1300 Data Book During 128 EVO clock cycles, the EVO block must have 2 requests acknowledged, that is, ([2Ys, 1U and 1V] / 2). For example, if the EVO clock is 27 MHz, then the EVO must get two requests ...
Page 129
Philips Semiconductors 2. Choose a value for PLL_S and PLL_T. For 8-40 MHz operation, a value of 1 (which selects division recommended. 3. Choose a value for CLOCK_SELECT. For 8-81 MHz operation, CLOCK_SELECT = 00 is recommended. ...
Page 130
TM1300 Data Book 7-26 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 131
Audio In 8.1 AUDIO IN OVERVIEW The TM1300 Audio In (AI) unit connects to an off-chip stereo A/D converter subsystem through a flexible bit-se- rial connection. The AI unit provides all signals needed to interface to high quality, low cost ...
Page 132
TM1300 Data Book AI_OSCLK (e.g. 256 AI_SCK (e. AI_WS Serial To Parallel Converter AI_SD Figure 8-1. AI clock system and I/O interface. 8.3 CLOCK SYSTEM Figure 8-1 illustrates the different clock capabilities of ...
Page 133
Philips Semiconductors (AI SER_MASTER=0, AI_SCK and AI_WS externally wired to the corresponding AO pins). In such systems, in- dependent software control over A/D and D/A sampling rate is not possible, but component count is minimized. Table 8-3.AI MMIO clock & ...
Page 134
TM1300 Data Book AI_SCK AI_WS AI_SD left (18) n Figure 8-3. Serial frame of the SAA7366 18 bit I sequent bits are assigned, in order, to increasing bit po- sitions in the LEFT data word, up ...
Page 135
Philips Semiconductors MMIO_base offset: 0x10 1C00 AI_STATUS (r/w) 0x10 1C04 AI_CTL (r/w) RESET CAP_ENABLE CAP_MODE SIGN_CONVERT LITTLE_ENDIAN 0x10 1C08 AI_SERIAL (r/w) SER_MASTER DATAMODE FRAMEMODE CLOCK_EDGE 0x10 1C0C AI_FRAMING (r/w) POLARITY 0x10 1C10 AI_FREQ (r/w) 0x10 1C14 AI_BASE1 (r/w) 0x10 1C18 ...
Page 136
TM1300 Data Book • set AI_FREQ to ensure that a valid clock is gener- ated (Only when AI is the master of the audio clock system) • MMIO(AI_CTL << 31; /* Software Reset */ • MMIO(AI_SERIAL ...
Page 137
Philips Semiconductors Table 8-8. AI MMIO status fields (read only) Field Name Description BUF2_FULL • If ‘1’, buffer 2 is full. If BUF2_INTEN is also ‘1’, an interrupt request (source 11) is pending. BUF2_FULL is cleared by writing a ‘1’ ...
Page 138
TM1300 Data Book 8-8 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 139
Audio Out 9.1 AUDIO OUT OVERVIEW The TM1300 Audio Out (AO) unit is new and contains many features not available in the TM1100. It has channels, and drives external stereo D/A con- verters through ...
Page 140
TM1300 Data Book 9.3 EXTERNAL INTERFACE Seven TM1300 pins are associated with the AO unit. The AO_OSCLK output is an accurately programmable clock output intended to be used as the master system clock for the external D/A subsystem. The other ...
Page 141
Philips Semiconductors AO_SCK AO_WS AO_SDx frame n-1 Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0) 9.5.2 TM1000 Clock Compatibility Mode TM1000 clock compatibility ...
Page 142
TM1300 Data Book Table 9-4. AO Serial Framing Control Fields Field Name Description POLARITY 0 serial frame starts with an AO_WS negedge (RESET default) 1 serial frame starts with an AO_WS posedge This bit should NOT be changed during operation ...
Page 143
Philips Semiconductors AO_SCK AO_WS AO_SDx left channel data (18) n Figure 9-3. Serial frame (64 bits 18-bit precision I 2 9.7 Serial Framing Example Refer to Figure 9-3 and Table 9-7 to ...
Page 144
TM1300 Data Book AO_SCK AO_WS AO_SDx lsb left channel data (16) n Figure 9-4. Example codec frame layout for a Crystal Semi, CS4218. Figure 9-4 shows a 64-bit frame suitable for use with the ...
Page 145
Philips Semiconductors MMIO_base offset: 0x10 2000 AO_STATUS (r/w) 0x10 2004 AO_CTL (r/w) RESET TRANS_ENABLE TRANS_MODE SIGN_CONVERT LITTLE_ENDIAN 0x10 2008 AO_SERIAL (r/w) SER_MASTER DATAMODE CLOCK_EDGE 0x10 200C AO_FRAMING (r/w) POLARITY 0x10 2010 AO_FREQ (r/w) 0x10 2014 AO_BASE1 (r/w) 0x10 2018 AO_BASE2 ...
Page 146
TM1300 Data Book • MMIO(AO_SERIAL << 31; /* sets serial-master mode, starts AO_SCK */ • MMIO(AO_SERIAL << 31) | (SCKDIV value); /* then set DIVIDER values */ Upon reset, transmission is disabled (TRANS_ENABLE = 0), and ...
Page 147
Philips Semiconductors Table 9-12. AO MMIO Control Fields Field Name Description RESET Resets the audio-out logic. See 9.10, “Audio Out Operation” tion of the recommended procedure. TRANS_ENABLE Transmission Enable flag. 0 (RESET default) AO inactive transmits samples and ...
Page 148
TM1300 Data Book Table 9-13. AO highway arbiter latency requirement examples max arbiter s TransMode (ns) latency (kHz) (ns) stereo 44.1 22,676 22,656 16 bits/sample stereo 48.0 20,833 20,813 16 bits/sample stereo 96.0 10,417 10,397 16 bits/sample 6 ...
Page 149
SPDIF Out 10.1 SPDIF OUT OVERVIEW The TM1300 SPDIF Output unit (SPDO) allows genera- tion of a 1-bit high-speed serial data stream. The primary application is to make SPDIF (Sony/Philips Digital Inter- face) data available for use by external audio ...
Page 150
TM1300 Data Book M sub-frame 1 W sub-frame 2 frame 191 Figure 10-2. Serial format of a IEC958 block 10.4 IEC-958 SERIAL FORMAT Figure 10-2 shows the serial format layout of a IEC-958 block. A block starts with a special ...
Page 151
Philips Semiconductors “1” “0” “0” “1” “1” UI cell B bi-phase mark violation M bi-phase mark violation W bi-phase mark violation Figure 10-3. Bi-phase mark data transmission ways starts with a rising edge. This is made possible thanks to the ...
Page 152
TM1300 Data Book Table 10-3. SPDIF sample rate setting f f FREQUENCY s DSPCPU (hexadecimal) (nSec) (kHz) (MHz) 32.000 143 0x80D0,9316 244.14 0.777 32.000 166 0x80B3,ACF8 244.14 0.669 32.000 180 0x80A5,B36E 244.14 0.617 44.100 143 0x811F,711B 177.15 0.777 44.100 166 ...
Page 153
Philips Semiconductors MMIO_base offset: 0x10 4C00 SPDO_STATUS (r/ 0x10 4C04 SPDO_CTL (r/w) RESET TRANS_ENABLE TRANS_MODE LITTLE_ENDIAN 0x10 4C08 SPDO_FREQ (r/w) 0x10 4C0C SPDO_BASE1 (r/w) 0x10 4C10 SPDO_BASE2 (r/w) 0x10 4C14 SPDO_SIZE (r/w) 0x10 4C18 SPDO_TSTAMP (r/o) Figure 10-4. SPDO unit ...
Page 154
TM1300 Data Book Table 10-5. SPDO_CTL MMIO register field type description SLEEPLESS If ‘1’, the SPDO block does not power down when TM1300 goes r/w into global power-down mode. If ‘0’, the block does power down. LITTLE_ENDIAN If asserted, the ...
Page 155
Philips Semiconductors Table 10-6. SPDO block highway latency requirements f Max. latency s (nSec) (kHz) 32.000 31250 44.100 22675 48.000 20833 10.18 LITERATURE REFERENCES [1] IEC-958 Digital Audio Interface, Part 1: General; Part 2: Professional applications; Part 3: Consumer applica- ...
Page 156
TM1300 Data Book 10-8 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 157
PCI Interface 11.1 NEW IN TM1300 TM1300 DMA read transactions use the more efficient ‘memory read multiple’ PCI transactions, unless explicit- ly disabled. Section 11.7.5. TM1300 contains an on-board PCI_CLK generator for low-cost configurations. It can be enabled/disabled at boot ...
Page 158
TM1300 Data Book 11.3 PCI INTERFACE AS AN INITIATOR The following classes of operations invoked by TM1300 cause the PCI interface to act as a PCI initiator: • Transparent, single-word (or smaller) transactions caused by DSPCPU loads and stores to ...
Page 159
Philips Semiconductors The PCI interface begins the PCI-bus transactions when software writes to DMA_CTL. As with the I/O and config- uration operations, the BIU_STATUS and BIU_CTL reg- isters monitor the status of the operation and control in- terrupt signaling. The ...
Page 160
TM1300 Data Book I/O (I/O access enable). This bit controls a device’s abil- ity to respond to I/O-space accesses. A value of ’0’ dis- ables PCI device response; a value of ’1’enables re- sponse. This bit is hardwired to ’0’ ...
Page 161
Philips Semiconductors Table 11-2. Field values for Command Register Field Value Explanation I/O Hardwired to 0 (ignore I/O space accesses recognition of memory-space accesses 1 recognizes memory-space accesses EM 0 cannot act as PCI initiator 1 can ...
Page 162
TM1300 Data Book • The initiator asserted perr# or detected it asserted by the target (during a write cycle). Table 11-3. Status register fields Field Characteristics Reserved Writes ignored; reads return 0 66M PCI bus speed (hardwired to 0 UDF ...
Page 163
Philips Semiconductors Table 11-6. Base Class Encodings Base Class Meaning (in hex) 00 Device was built before class code definitions were finalized 01 Mass-storage controller 02 Network controller 03 Display controller 04 Multimedia device 05 Memory controller 06 Bridge device ...
Page 164
TM1300 Data Book In X86 or other host-assisted platforms, the PCI host as- sisted boot sequence is executed. In this case, the base registers are not set from the EEPROM. Instead, the host BIOS executes a scan for devices on ...
Page 165
Philips Semiconductors location of these bits is described in tailed EEPROM Contents.” A legal Vendor ID must be obtained from the PCI SIG. The vendor is free to assign subsystem ID’s. 11.6.13 Expansion ROM Base Address Register The Expansion ROM ...
Page 166
TM1300 Data Book • writing to SDRAM_BASE moves the origin of any executing DSPCPU program, which will cause it to fail • writing to MMIO_BASE moves devices around, and moves MMIO_BASE and SDRAM_BASE around • writing to both registers in ...
Page 167
Philips Semiconductors while a request of similar type is in progress, the PCI in- terface ignores the second command and sets the ap- propriate error bit in the status register. When the DSPCPU issues either an io_cycle or config_cycle request ...
Page 168
TM1300 Data Book IE (ICP DMA enable).This bit is must be set to ’1’ to allow the ICP to write pixel data through the PCI interface. If this bit is cleared to ’0’, the ICP is not allowed to use ...
Page 169
Philips Semiconductors PCI bus and devices. The DSPCPU writes or reads CONFIG_DATA depending on whether it is performing a write or read to a PCI device’s configuration space. See Section 11.7.10, “CONFIG_CTL Register,” formation on initiating configuration cycles. 11.7.10 CONFIG_CTL ...
Page 170
TM1300 Data Book Following are descriptions of the fields of IO_CTL and a discussion of how a DSPCPU write to IO_CTL triggers I/ O cycles. BE (Byte enables). The BE field (the four least-signifi- cant bits of IO_CTL) determines the ...
Page 171
Philips Semiconductors is decremented, and this sequence repeats until TL reaches ‘0’. At the end of the PCI SDRAM block transfer, the PCI interface will generate a DSPCPU interrupt if the appro- priate IntE bit is set in BIU_CTL. Alternatively, ...
Page 172
TM1300 Data Book pci_clk frame# ad Address c/be# Byte Enables Command irdy# trdy# devsel# Figure 11-10. Basic single-data-phase read opera- asserts the frame# signal to indicate that the transaction has begun and that an address and command ...
Page 173
Philips Semiconductors 1 2 pci_clk frame# ad Address c/be# Command irdy# trdy# devsel# Figure 11-13. Back-to-back PCI burst write operations with 16 data phases which might be generated by the ICP when writing image data to a PCI-resident video frame ...
Page 174
TM1300 Data Book 11-18 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 175
SDRAM Memory System 12.1 NEW IN TM1300 • Support of 64-Mbit SDRAMs organized in x16 and 128-Mbit organized in x32. • Partial support of 64-Mbit SDRAMs organized in x8 and 128-Mbit SDRAMs organized in x16. • External MM_MATCHOUT to MM_MATCHIN ...
Page 176
TM1300 Data Book TM1300 TM1300 Memory Interface DSPCPU Data Highway On-Chip Peripherals Figure 12-1. A high-performance memory interface connects the TM1300 internal highway bus to external SDRAM or SGRAM. The interface is glueless for an array four ...
Page 177
Philips Semiconductors MMIO_base offset: 0x10 0100 MM_CONFIG (r/o) 0x10 0300 PLL_RATIOS (r/o) Figure 12-2. Memory interface configuration registers. External Clock Input TRI_CLKIN Memory System Clocks MM_CLK1 MM_CLK0 Figure 12-3. TM1300 memory and core PLL connections. 12.6 MEMORY SYSTEM PROGRAMMING Memory ...
Page 178
TM1300 Data Book Table 12-3. Examples of Memory Configurations Size Ranks Rank Configurations (MB four SDRAM 2 two 2 512K 16 SDRAM two 2 512K 16 SDRAM 1 one 4 512K 32 SDRAM 16 1 ...
Page 179
Philips Semiconductors 12.7 MEMORY INTERFACE PIN LIST The memory interface consists of 61 signal pins includ- ing clocks (but excluding power and ground pins). Table 12-7 lists the interface signal pins. Table 12-7. Memory Interface Signal Pins Name Function MM_CLK[1:0] ...
Page 180
TM1300 Data Book The benefit of on-chip interleaving is sustainable full- bandwidth data transfer (1 word per clock cycle). The transition from one internal bank to the other happens on 8-word boundaries; transferring 8 words gives the inac- tive bank ...
Page 181
Philips Semiconductors TM1300 TM1300 Memory Interface DSPCPU Data Highway On-Chip Peripherals Figure 12-4. Conceptual board layout. Table 12-11. Glueless interface limits for address/ clocks Memory Chips Maximum Clock Frequency 4 143 MHz 6 133 MHz 8 133 MHz capacitance. Close ...
Page 182
TM1300 Data Book and a T for TM1300 less or equal than 0.4 ns. In other SU words the following equation needs to be met cycle AC board CS Where T is ...
Page 183
Philips Semiconductors MM_CLK[1] MM_CS#[1] MM_CLK[1] MM_CS#[1] MM_CLK[0] MM_CS#[0] MM_CLK[0] MM_CS#[0] Figure 12-6. Schematic of a 32-MB memory system consisting of four SDRAM chips (two ranks) details a 32-MB memory system. Removing the device controlled by MM_CS#[1] makes ...
Page 184
TM1300 Data Book MM_CLK[0] MM_CS#[0] Figure 12-7. Schematic of a 8-MB memory system consisting of one 4 512K 32 SDRAM (one rank). shows an 8-MB memory system (one device only) and Figure 12-8 a 16-MB configuration. SDRAMs organized in x16 ...
Page 185
Philips Semiconductors MM_CLK[1] MM_CS#[0] MM_CLK[0] MM_CS#[1] Figure 12-8. Schematic of a 16-MB memory system consisting of two ranks of 4 512K 32 SDRAM chips. TM1300 4 512K 32 BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[10:0] MM_DQM[3:0] Control DQM[3:0] CS# 4 512K ...
Page 186
TM1300 Data Book the unusual way of using the devices the only sup- ported configuration with x8 devices. MM_CONFIG.SIZE must be set to 6 (i.e. 16-MB rank size, MM_CLK[1] MM_CLK[1] MM_CLK[0] MM_CLK[0] Figure 12-9. Schematic of a 32-MB ...
Page 187
Philips Semiconductors Figure 12-10 for a more detailed connection scheme. MM_CONFIG.SIZE must be set to 6 (i. rank MM_CLK[0] MM_CLK[1] Figure 12-10. Schematic of a 32-MB memory system consisting of two SDRAM chips (one rank) ...
Page 188
TM1300 Data Book MM_CLK[1] MM_CS#[0] MM_CLK[0] MM_CS#[1] Figure 12-11. Schematic of a 32-MB memory system consisting of two ranks SDRAM chips. 12-14 PRODUCT SPECIFICATION TM1300 BA[1:0] SDRAM MM_DQ[31:0] CLK DQ[31:0] Address[11:0] MM_DQM[3:0] Control ...
Page 189
System Boot 13.1 NEW IN TM1300 A new bit in the boot EEPROM allows an internal PCI_CLK clock source for low-cost standalone systems 13.2 TM1300 BOOT SEQUENCE OVERVIEW Before a TM1300 system can begin operating, the main- memory interface (MMI) ...
Page 190
TM1300 Data Book 13.3 BOOT HARDWARE OPERATION The TM1300 boot sequence begins with the assertion of the reset signal TRI_RESET#. After reset is de-asserted, 2 only the system boot block and PCI interfaces are allowed to operate. In ...
Page 191
Philips Semiconductors system Vendor ID Register,” for more information on the choice of values. 2 Table 13-3I C speed as a function of EEPROM byte 0 BOOT_CLK EEPROM divider bits speed bit value 00 (100 MHz) 0 (100 KHz) 1008 ...
Page 192
TM1300 Data Book TRI_RESET# de-asserted Wait ca. 0.6 msec for stabilize 8-bit serial read: 1 bit: EPROM capacity 3 bits: DRAM aperture size 2 bits: TM1300 clock speed 2 1 bit clock rate 1 ...
Page 193
Philips Semiconductors 13.3.2 Initial DSPCPU Program Load for Autonomous Bootstrap In a system where TM1300 serves as the host CPU, the system boot block performs an autonomous boot proce- dure. For an autonomous boot, the system boot block reads all ...
Page 194
TM1300 Data Book gram can consist 500 32-bit words of DSPCPU instructions. The byte count must be a multiple of four. Note that the bytes are stored in the EEPROM in a byte swapped order per group ...
Page 195
Philips Semiconductors 13.5 DETAILED EEPROM CONTENTS Table 13-5 shows the serial EEPROM contents needed for an autonomous boot procedure. For the host-assisted Table 13-5. Serial boot EEPROM contents Line bit 7 bit 6 SDRAM size[2:0] #lines 0: 128 lines 0 ...
Page 196
TM1300 Data Book Table 13-5. Serial boot EEPROM contents Line bit 7 bit byte 0 of DSPCPU bootstrap program (stored at DRAM_BASE + 3) 48 byte 1 of DSPCPU bootstrap ...
Page 197
Philips Semiconductors 13.6 EEPROM ACCESS PROTOCOLS Figure 13-3 shows the SDA (serial data) line protocols for three types of read accesses supported by I EEPROMs. A read from the address currently latched in- side the EEPROM can be for either ...
Page 198
TM1300 Data Book 13-10 PRODUCT SPECIFICATION Philips Semiconductors ...
Page 199
Image Coprocessor 14.1 IMAGE COPROCESSOR OVERVIEW The Image Coprocessor (ICP) connects to the TM1300 on-chip data highway to perform SDRAM block read and write actions. It also connects to the PCI interface to al- low block write transactions across PCI. ...
Page 200
TM1300 Data Book Digital Camera DMSD or Raw Video DMA In Video Audio DMA In Serial Digital Audio Audio DMA Out DSPCPU JTAG Clock Figure 14-1. TM1300 chip block diagram Y U FIFO Bank V Overlay Bit Mask To SDRAM ...