CY7C4271-10AC Cypress Semiconductor Corporation., CY7C4271-10AC Datasheet
CY7C4271-10AC
Related parts for CY7C4271-10AC
CY7C4271-10AC Summary of contents
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... Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width-Expansion Capability • Military temp SMD Offering – CY7C4271-15LMB • 32-pin PLCC/LCC and 32-pin TQFP • Pin-compatible density upgrade to CY7C42X1 family • Pin-compatible density upgrade to ...
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... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Description 7C4261/71-15 7C4261/71-25 100 66 0 CY7C4261 CY7C4271 7C4261/71-35 Unit 28.6 MHz Page [+] Feedback ...
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... Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. CY7C4261 CY7C4271 32K × Empty Offset (LSB) Reg. ...
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... PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration Document #: 38-06015 Rev. *C RESET (RS) 9 CY7C4261/ Read Enable 2 (REN2) CY7C4261 CY7C4271 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 DATA OUT ( Page ...
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... Ind/Mil 40 Com’l 10 Ind/Mil 15 Test Conditions ° MHz 5.0V CC [10, 11] 3.0V GND R2 ≤3 ns 680Ω 1.91V . CY7C4261 CY7C4271 + 0.5V CC Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C ° ° −55 5V ± 10 +125 C Max. ...
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... CY7C4261 CY7C4271 Min. Max. Min. Max. Unit 40 28.6 MHz ...
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... NO OPERATION t REF t REF t A VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261 CY7C4271 NO OPERATION NO OPERATION t OHZ Page [+] Feedback ...
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... RSR RSS t RSF t RSF t RSF [19] t FRL t REF [20 OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4261 CY7C4271 [17 (maximum) = either 2 FRL CLK SKEW1 CLK Page [+] Feedback ...
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... ENH WEN2 (if applicable) [19] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06015 Rev DATA WRITE 2 t ENS t ENS REF REF SKEW1 t A CY7C4261 CY7C4271 t ENH t ENH [19] t FRL t REF DATA READ Page [+] Feedback ...
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... Document #: 38-06015 Rev SKEW1 DATA WRITE t WFF DATA READ t CLKL t ENS ENH t ENS ENH Note 22 [21] t PAE t ENS CY7C4261 CY7C4271 NO WRITE [14] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ WORDS Note 23 IN FIFO t PAE t t ENS ENH Page [+] Feedback ...
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... If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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... V 0.80 A 0.60 −55.00 4.50 5.00 5.50 6.00 AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) CY7C4261 CY7C4271 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB vs. AMBIENT A = 5.0V CC 5.00 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1. 25°C 0. 3.0V IN 0.50 20 ...
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... CY7C4261-15AC CY7C4261-15JC CY7C4261-15JXC CY7C4261-15AI CY7C4261-15JI 25 CY7C4261-25AC CY7C4261-25JC CY7C4261-25AI CY7C4261-25JI 35 CY7C4261-35AC CY7C4261-35JC CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI CY7C4271-10JI 15 CY7C4271-15AC CY7C4271-15JC CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB 5962-9736101QYA 25 CY7C4271-25AC CY7C4271-25JC CY7C4271-25AI CY7C4271-25JI 35 CY7C4271-35AC CY7C4271-35JC CY7C4271-35AI CY7C4271-35JI Document #: 38-06015 Rev. *C ...
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... WEF t WFF t WHF t RHF t RAE t RPE t WAF t WPF t XOL t XOH CY7C4261 CY7C4271 Subgroups 10, 11 ...
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... Package Diagrams 32-Lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 32-Lead Pb-Free Plastic Leaded Chip Carrier J65 Document #: 38-06015 Rev. *C 32-Lead Plastic Leaded Chip Carrier J65 CY7C4261 CY7C4271 51-85063-*B 51-85002-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. MIL-STD-1835 C-12 51-80068-** CY7C4261 CY7C4271 Page [+] Feedback ...
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... Document History Page Document Title: CY7C4261, CY7C4271 16K/32K X 9 Deep Synchronous FIFOs Document Number: 38-06015 REV. ECN NO. Issue Date ** 106476 09/10/01 *A 122267 12/26/02 *B 127853 08/22/03 *C See ECN 393437 Document #: 38-06015 Rev. *C Orig. of Change Description of Change SZV Changed from Spec number: 38-00658 to 38-06015 RBI Added power-up requirements Maximum Ratings Information ...