CY7C4271-15LMB Cypress Semiconductor Corporation., CY7C4271-15LMB Datasheet

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CY7C4271-15LMB

Manufacturer Part Number
CY7C4271-15LMB
Description
CY7C4271-15LMB16K/32K x 9 Deep Sync FIFOs
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-06015 Rev. *B
Features
• High-speed, low-power, first-in first-out (FIFO)
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power — I
• Fully asynchronous and simultaneous read and write
• Empty, Full, Half Full, and programmable Almost Empty
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
memories
times)
operation
and Almost Full status flags
IDT72201/11/21/31/41/51
RS
Logic Block Diagram
WCLK
CONTROL
POINTER
WEN1
WRITE
WRITE
RESET
LOGIC
CC
WEN2/LD
= 35 mA
OUTPUT REGISTER
THREE-STATE
REGISTER
ARRAY
16K x 9
32K x 9
INPUT
Q
D
RAM
0
0
8
8
OE
3901 North First Street
RCLK
PROGRAM
REGISTER
CONTROL
POINTER
LOGIC
FLAG
READ
READ
FLAG
REN1 REN2
Pin Configuration
Functional Description
The
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
16K/32K x 9 Deep Sync FIFOs
EF
PAE
PAF
FF
CY7C4261/71
REN1
RCLK
REN2
GND
PAE
PAF
D
D
1
0
San Jose
REN1
RCLK
REN2
GND
PAE
PAF
OE
D
D
1
0
1
2
3
4
5
6
7
8
32
9 10 11 12 13
5
6
7
8
9
10
11
12
13
are
14 15 16 17 18 19 20
4 3 2 1
31 30
,
PLCC/LCC
CA 95134
CY7C4261
CY7C4271
Top View
CY7C4261
CY7C4271
Top View
high-speed,
TQFP
29 28 27
32
14 15 16
31 30
Revised August 21, 2003
26
29
28
27
26
25
24
23
22
21
25
24
23
22
21
20
19
18
17
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
low-power
CC
8
7
6
5
CY7C4261
CY7C4271
408-943-2600
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
FIFO

Related parts for CY7C4271-15LMB

CY7C4271-15LMB Summary of contents

Page 1

... Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width-Expansion Capability • Military temp SMD Offering – CY7C4271-15LMB • 32-pin PLCC/LCC and 32-pin TQFP • Pin-compatible density upgrade to CY7C42X1 family • Pin-compatible density upgrade to ...

Page 2

... When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. 7C4261/71-10 7C4261/71-15 100 66 0 CY7C4261 CY7C4271 Description 7C4261/71-25 7C4261/71- Page ...

Page 3

... Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) (PAF) states are deter- mined by their corresponding offset registers and the difference between the read and write pointers. CY7C4261 CY7C4271 16K × 9 32K × Empty Offset (LSB) Reg ...

Page 4

... PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...

Page 5

... Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration Document #: 38-06015 Rev. *B RESET (RS) 9 CY7C4261/ Read Enable 2 (REN2) CY7C4261 CY7C4271 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF DATA OUT (Q) 9 ...

Page 6

... Com’l 35 Ind/Mil 40 Com’l 10 Ind/Mil 15 Description Test Conditions MHz 5.0V CC [10, 11] 3.0V GND R2 680 1.91V . OHZ CY7C4261 CY7C4271 Ambient Temperature + +125 C Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.0 V 2 2.2 V 2 ...

Page 7

... CY7C4261 CY7C4271 Max. Min. Max. Min. Max. 66.7 40 28.6 MHz ...

Page 8

... REF [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261 CY7C4271 ENH NO OPERATION NO OPERATION t WFF t REF VALID DATA t OHZ Page ...

Page 9

... RSS t RSS t RSF t RSF t RSF D 1 [19] t FRL t SKEW1 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4261 CY7C4271 t RSR t RSR t RSR [17 OE [20 (maximum) = either 2 FRL CLK SKEW1 Page ...

Page 10

... DATA IN OUTPUT REGISTER 0 8 Document #: 38-06015 Rev. *B [19 REF REF DATA WRITE t WFF t ENH t A DATA READ CY7C4261 CY7C4271 t DS DATA WRITE 2 t ENH t ENS t t ENH ENS [19] t FRL t t SKEW1 DATA READ NO WRITE [14] t SKEW1 ...

Page 11

... PAE Note t CLKL ENS ENH Note PAF ENS ENH (M+1)WORDS IN FIFO (m 1) words of the FIFO when PAF goes LOW. m words for CY7C4271. CY7C4261 CY7C4271 WORDS Note IN FIFO ENS ENS ENH FULL MWORDS [26] IN FIFO [27 PAF ...

Page 12

... Document #: 38-06015 Rev CLKL t ENH PAE OFFSET PAE OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4261 CY7C4271 PAF OFFSET PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB Page ...

Page 13

... Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier A32 32-Lead Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier A32 32-Lead Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier CY7C4261 CY7C4271 NORMALIZED t vs. AMBIENT A TEMPERATURE V =5.0V CC 55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE( C) NORMALIZED SUPPLY CURRENT vs ...

Page 14

... Ordering Code 35 CY7C4261-35AC CY7C4261-35JC CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI CY7C4271-10JI 15 CY7C4271-15AC CY7C4271-15JC CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB 5962-9736101QYA 25 CY7C4271-25AC CY7C4271-25JC CY7C4271-25AI CY7C4271-25JI 35 CY7C4271-35AC CY7C4271-35JC CY7C4271-35AI CY7C4271-35JI MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters ...

Page 15

... RFF t 9, 10, 11 WEF t 9, 10, 11 WFF t 9, 10, 11 WHF t 9, 10, 11 RHF t 9, 10, 11 RAE t 9, 10, 11 RPE t 9, 10, 11 WAF t 9, 10, 11 WPF t 9, 10, 11 XOL t 9, 10, 11 XOH Document #: 38-06015 Rev. *B Subgroups CY7C4261 CY7C4271 Page ...

Page 16

... Package Diagrams 32-Lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 Document #: 38-06015 Rev. *B 32-Lead Plastic Leaded Chip Carrier J65 CY7C4261 CY7C4271 51-85063-*B 51-85002-*B Page ...

Page 17

... Package Diagrams (continued) All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06015 Rev. *B 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 CY7C4261 CY7C4271 51-80068-** Page ...

Page 18

... Document History Page Document Title: CY7C4261, CY7C4271 16K/32K X 9 Deep Synchronous FIFOs Document Number: 38-06015 REV. ECN NO. Issue Date ** 106476 09/10/01 *A 122267 12/26/02 *B 127853 08/22/03 Document #: 38-06015 Rev. *B Orig. of Change SZV Changed from Spec number: 38-00658 to 38-06015 RBI Added power-up requirements Maximum Ratings Information ...

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