SAA7893HL NXP Semiconductors, SAA7893HL Datasheet
SAA7893HL
Available stocks
Related parts for SAA7893HL
SAA7893HL Summary of contents
Page 1
... SACD functionality. Philips' Super Audio Media Player (SA-MP) provides a flexible, state-of-the-art solution for SACD playback on DVD architectures. Built around the SAA7893HL SACD processor, SA-MP system solution delivers complete SACD functionality, avoiding the need for continual redesign and re-integration of SACD into various applications. The system is completed with a ...
Page 2
... DVD system incorporating the SAA7893HL is shown in The SAA7893HL takes sector data from the front-end. The front-end is controlled by the DVD host via the SA-MP software stack. The SAA7893HL uses one 64 Mbit SDRAM for audio data buffering and storage of SACD TOCs. The front-end timing can be fully asynchronous from all clocks ...
Page 3
... DRIVERS SAA7893HL HW Fig 3. Software block diagram. 2. Features 2.1 Components SAA7893HL second generation SACD processor IC SA-MP Annex J+ level software stack. 2.2 HW interfaces Front-end, supports 3 types: Flexible PSP detection from EFM signal with AGC, without EFM clock (digital PLL) (DVD-)host bus, supports 3 types: 16-bit 100 MHz SDRAM interface supports one 64 Mbit device ...
Page 4
... Repeat (Track, All or AB) Shuffle Introscan Time search Dolby® configuration 0 (LLL1) Dolby® configuration 1 (SSS1) Dolby® configuration 2 (LSS0) Rev. 02 — 26 February 2003 SAA7893HL Super audio media player © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 5
... PCM to DSD upsampling with 3 programmable Sigma-Delta and anti-aliasing filter modes Attenuation and delay as with DSD Rev. 02 — 26 February 2003 SAA7893HL Super audio media player © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 6
... DECODER INTERFACE key control data-bus DECRYPTION/ SECTOR PROCESSOR PI-BUS CONTROL Fig 4. Block diagram. 9397 750 10925 Product data shows the block diagram of the SAA7893HL with all defined functions. to host HOST INTERFACE REGISTER HOST INTERFACE MEMORY MANAGER PI-bus DEMUX SACD 6-channel ...
Page 7
... PCM_wclk_in 31 V DDA 32 V SSA 33 biasin 34 Agcinp 35 Adcrefl 36 VCC_IO7 37 GND_IO7 38 Fig 5. Pin configuration. 9397 750 10925 Product data SAA7893HL Rev. 02 — 26 February 2003 SAA7893HL Super audio media player 102 D_DQ[13] 101 D_DQ[2] 100 D_DQ[12] 99 GND_IO5 98 D_DQ[3] 97 D_DQ[11] 96 D_DQ[4] 95 D_DQ[10] 94 D_DQ[9] 93 ...
Page 8
... APIO ADC decoupling 37 VCC_IO V 38 GND_IO GND I/O pads 39 IN PCM data center or LFE Rev. 02 — 26 February 2003 SAA7893HL Super audio media player I/O pads CC of ADC DD of AGC and ADC; connected to substrate SS I/O pads CC © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 9
... IN I host host request data from front-end; routed via the SAA7893HL 48 O10 data request for UDE 49 IN front-end parallel data interface 50 IN front-end parallel data interface 51 IN front-end parallel data interface 52 IN front-end parallel data interface ...
Page 10
... O10 6-channel data output 115 O10 6-channel clock/control 116 O10 6-channel clock/control 117 O10 2-channel clock/control 118 VCC_IO V Rev. 02 — 26 February 2003 SAA7893HL Super audio media player I/O pads CC I/O pads CC I/O pads CC © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 11
... Separate address/data bus with 8-bit data bus (1 mode). The host interface type is set via the dedicated pins H_sel and sys_clk. The SAA7893HL has a dedicated interrupt output pin. 7.2 Front-end interface 7.2.1 Data input interface The SAA7893HL supports three different front-end interfaces which are selectable via the host interface: • ...
Page 12
... Parallel interface (UDE data interface part): a parallel front-end interface with a handshake protocol. 7.2.2 Analog HF input The analog HF input, coming from the optical pickup unit, is also fed to the SAA7893HL to extract the copy protection information PSP. 7.3 Audio interface 7.3.1 Audio input The audio input is a 6-channel PCM-I 7 ...
Page 13
... Product data T clk t clk(l) t clk( Conditions clock frequency from MHz T clk t clk(l) t clk( Conditions clock frequency from 256 to 768 48 kHz Rev. 02 — 26 February 2003 SAA7893HL Super audio media player MDB146 Min Max Unit 28.5 37.4 ns 11.4 22.4 ns 11.4 22 ...
Page 14
... Philips Semiconductors Manufacturer ID: B000 0001 0101 Part no: B0011 0101 0110 0100. 8. Host interface 8.1 General description The SAA7893HL is capable to communicate with the hosts (families) via their own busses as given in Table 5: Name SAD16_01 SAD16_02 SAD16_03 MAD16_01 MAD16_02 SAD08 The type of host is selected via two input pins H_sel[1] and H_sel[0] and the proc_clk signal ...
Page 15
... SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter called ‘the base address’ into the SAA7893HL. Therefore, to access an address inside the SAA7893HL first these 16 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host device ...
Page 16
... Timing numbers of writing registers with no wait cycles Parameter total CSn time set-up time from CS to host control/address lines hold time from CS to host control/address lines Rev. 02 — 26 February 2003 SAA7893HL Super audio media player t h MBL622 Min Typ Max Unit ...
Page 17
... Fig 11. Timing diagram of writing registers with wait cycles. 9397 750 10925 Product data t tot t tri Z undefined t set Conditions maximum time is not needed; can be forever t tot wt(st) Rev. 02 — 26 February 2003 SAA7893HL Super audio media player h(D) Z data MBL633 Min Typ Max Unit sys_clk ...
Page 18
... H_WAIT inactive until CS becomes inactive wt(en) [1] When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles. 8.2.4 Read mode: cycles extended using wait protocol H_CSn t su ...
Page 19
... When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal of at least 7 sys_clk cycles, then longer required that the minimum time the H_WAIT signal. The host can deactivate the H_CS signal after the negative edge of the H_WAIT signal and when it has read the data at the H_DQ lines ...
Page 20
... H_CSn H_A_sel H_RWn H_A[6:1] H_DQ[15:0] Fig 14. Write to or read from the SAA7893HL. In Figure 14 here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is of course not to scale. When the base address is written, multiple accesses can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way a burst of 64 Hwords can be read or written to the same address ...
Page 21
... First the 16 bits of the base address are set indicated by the H_A_sel line. Then a read access is started. In SAD16_03 mode there is no handshake line on which the SAA7893HL can indicate that internal read operation is ready. Therefore sure that the requested data is read correctly, an extra read is needed indicated by the H_A_sel line ...
Page 22
... Philips Semiconductors 8.3.2 Write mode H_CSn H_A_sel H_RWn H_A[6:1] H_DQ[15:0] Fig 16. Write to the SAA7893HL. When a write operation is issued the same wait time t before a next access may start, but here no double write has to be done. 8.3.3 Writing of base address H_CSn t su(rw) H_RWn H_A_sel t su(ad) H_A[6:1] H_DQ[15:0] Fig 17 ...
Page 23
... Writing data to the SAA7893HL H_CSn t su(rw) H_RWn H_A_sel t su(ad) H_A[6:1] H_DQ[15:0] Fig 18. Writing data to the SAA7893HL. Table 13: Timing numbers of writing data Symbol Parameter t total LOW time of H_CSn tot t wait time before next cycle may start wt t set-up time of H_RWn ...
Page 24
... Philips Semiconductors 8.3.5 Reading data from the SAA7893HL H_CSn t su(rw) H_RWn H_A_sel t su(ad) H_address(6:1) t d(tri) Z H_data Fig 19. Reading data from the SAA7893HL. Table 14: Timing numbers of reading data Symbol Parameter t total LOW time of H_CSn tot t wait time before next cycle may start wt t set-up time of H_RWn ...
Page 25
... Host interface connection Fig 20. Host interface connection. 8.4 MAD16_01 mode Data communication is here always done on a 16-bit data bus. The address is mapped on 6 separate address pins and 16 address/data pins of the SAA7893HL. Therefore, in this mode the complete address is transferred directly in each access cycle. In Table 7 pins: Fur_H_A[22:1] = H_A[6:5] & ...
Page 26
... Philips Semiconductors 8.4.1 Write mode: minimum cycle sys_clk H_CSn H_A_sel H_RWn H_WAIT addr H_A[6:1] addr H_DQ[15:0] Fig 21. Timing diagram writing to the SAA7893HL. Table 15: Symbol t tot su(D) 9397 750 10925 Product data t tot Timing numbers of writing registers ...
Page 27
... Philips Semiconductors 8.4.2 Read mode: minimum cycle sys_clk H_CSn H_A_sel H_RWn H_WAIT addr H_A[6:1] addr H_DQ[15:0] Fig 22. Timing diagram reading from the SAA7893HL. Table 16: Timing numbers of reading registers Symbol Parameter t set-up time H_A_sel su t hold time of H_A_sel with respect to h sys_clk t ...
Page 28
... Write mode: cycles extended using wait protocol sys_clk H_CSn H_A_sel H_RWn H_WAIT addr H_A[6:1] addr H_DQ[15:0] Fig 23. Timing diagram writing to the SAA7893HL (with wait cycles). Table 17: Timing numbers of writing registers (with wait cycles) Symbol Parameter t total H_CSn time tot t set-up time H_A_sel su t ...
Page 29
... Read mode: cycles extended using wait protocol sys_clk H_CSn H_A_sel H_RWn H_WAIT addr H_A[6:1] addr H_DQ[15:0] Fig 24. Timing diagram reading from the SAA7893HL (with wait cycles). Table 18: Timing numbers of reading registers (with wait cycles) Symbol Parameter t total H_CSn time tot t set-up time H_A_sel su t ...
Page 30
... AD(21:16) H_A[6: 11, 12, 13, 14, 15, 16, 22, 23, 25 AD(15:0) H_DQ[15:0] 21 SCLK sys_clk 28 IRQ_x H_IRQn 18 GND_IO H_procclk 62 VCC_IO H_sel[0] 63 VCC_IO H_sel[1] Rev. 02 — 26 February 2003 SAA7893HL Super audio media player SAA7893HL MCE046 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 31
... H_A_sel line. 8.5.1 Write mode H_CSn H_A_sel t h(ad) H_RWn ha[22:20] H_A[3:1] H_DQ[15:0] ha[19:4] H_WAITn Fig 27. Timing diagram writing to the SAA7893HL. 9397 750 10925 Product data ha[3:1] Z undefined Figure 26 not needed that the provided system clock tot t su ha[3:1] data[15:0] ...
Page 32
... Read mode H_CSn H_A_sel t h H_RWn ha[22:20] H_A[3:1] H_WAITn H_DQ[15:0] ha[19:4] Fig 28. Timing diagram reading from the SAA7893HL. Table 20: Symbol t tot dw1 9397 750 10925 Product data Timing numbers of MAD16_02 write Parameter total LOW time of H_CSn hold time of address/data with respect to ...
Page 33
... SAA7893HL. The internal SAA7893HL communication stays on 16-bit. Therefore, the host interface block ‘translates’ the 8 bits external communication to the 16 bits internal. To save physical pins on the SAA7893HL device, the data bus and 4 address bits are used to write the 12 MSB address bits, hereafter called ‘the base address’, into the SAA7893HL device. Therefore, to access an address inside the SAA7893HL fi ...
Page 34
... Writing to the SAA7893HL A write to address bits to the SAA7893HL will be translated to two byte accesses. First the LSB byte is written to address N [so A(0) = logic 0] and stored in cache. Then the MSB byte is written to address N+1 [so A(0) = logic 1]. When the ...
Page 35
... H_CSn H_DQ[11:8] H_A[7: H_RWn t d(as) H_DQ[13] H_DQ[7:0] t d(ds) H_DQ[14] H_WAIT Fig 31. Timing diagram SAD08 write to SAA7893HL. Table 21: Timing numbers of SAD08 write Symbol Parameter t set-up time from H_CSn, H_RWn and su H_DQ(13) to sys_clk t hold time from clk to H_CSn, H_RWn h and H_DQ(13) t ...
Page 36
... H_CSn H_DQ[11:8] H_A[7: H_RWn H_DQ[13] H_DQ[7:0] H_DQ[14] H_WAIT Fig 32. Timing diagram SAD08 read from the SAA7893HL. Table 22: Timing numbers of SAD08 read Symbol Parameter t set-up time from H_CSn, H_RWn su and H_DQ[13] to sys_clk t hold time from clk to H_CSn, H_RWn h ...
Page 37
... The interrupt output is a LOW level interrupt which must be connected to the interrupt input of the DVD host. 9. Front-end interface First the SACD sector structure is explained and how to connect the SAA7893HL in the different modes. For these different modes the interface timing figures will be given. ...
Page 38
... Philips Semiconductors Byte HEADER 12 Byte 0 Byte INFORMATION ID[31...24] Fig 34. SACD sector format. The SAA7893HL supports a data input bit rate of maximal 40 Mbits/s. The connections to the SAA7893HL in the different front-end modes are given in Table Table 23: SAA7893HL name B_FLAG B_SYNC B_WCLK B_BCLK B_DATA ...
Page 39
... Fig 35. Front-end input timing. When the B_SYNC signal is set to logic 1 between bit position D15 and D11 the SAA7893HL accepts this word as the start of a sector. The SAA7893HL does not perform EDC checking on the main data, but is dependent on the B_FLAG. A sector is set to erroneous if B_FLAG is set to logic 1. ...
Page 40
... Product data 2 I S-BUS SAA7893HL front-end IC 46 B_BCLK I2S_clk 44 I2S_wclk B_WCLK 43 I2S_sync B_SYNC 42 I2S_err B_FLAG 45 I2S_dat B_DATA 49-55 Be_dat(7:1) 47 open UDE_req 48 Data_req or GND. CC Section 9.2.1) Rev. 02 — 26 February 2003 SAA7893HL Super audio media player MCE053 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 41
... Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable. The UDE transmitter must react on the Data_req signal within 5 B_BCLK cycles. The SAA7893HL samples the data on the positive slope of B_BCLK when the B_WCLK signal is active. When B_FLAG signal is active for one byte of the sector, the total sector will be treated as erroneous ...
Page 42
... Conditions maximum clock frequency of B_BCLK is 20 MHz data/control must be stable during t before positive slope of B_BCLK data/control must be kept at least during t after positive slope of B_BCLK h Rev. 02 — 26 February 2003 SAA7893HL Super audio media player MCE055 Min Max Unit ...
Page 43
... UDE_req req sdclk senb sync serr data bit bit bit bit bit Rev. 02 — 26 February 2003 SAA7893HL Super audio media player SAA7893HL DVD back-end IC with UDE MCE056 bit bit bit bit bit bit bit bit Figure 41. The fi ...
Page 44
... On every SACD disc a PSP signal must be recorded. The player is only allowed to play a disc if a valid PSP signal is detected. This PSP key is recorded via a special mechanism in the EFM signal on disc. The EFM+ signal must be fed to the SAA7893HL as shown in 9397 750 10925 Product data ...
Page 45
... SA-MP settings are that a pit on the disc must have a higher output voltage than the land. The EFM+ input signal has no timing requirements with respect to the digital input of the front-end interface of the SAA7893HL. The SAA7893HL supports also an inversion of the EFM+ signal. 10.2 HF input specification The AGC circuit must be able to handle the following signal characteristics of the HF input signal ...
Page 46
... Section 11.1.1 Audio input directly coupled When no processing is done inside the SAA7893HL with respect to the I input stream, this input stream is sent via a multiplexer to the I no clocking is done on this signal, meaning that also no locked audio clock needs to be present ...
Page 47
... I2S_clk PCM_dclk_in 31 I2S_wclk PCM_wclk_in 40 I2S_leri PCM_LeRi_in 39 I2S_Celfe PCM_CeLf_in 41 PCM_LsRs_in I2S_Isrs Table 31. Rev. 02 — 26 February 2003 SAA7893HL Super audio media player left channel left surround center MSB MBL628 Min Unit MCE059 2 S format. The © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 48
... Philips Semiconductors The SAA7893HL has 12 output lines: 8 lines are allocated for connection to a 6-channel DAC and 4 are for connection to a 2-channel DAC reference signal. The DSD data on the MCH output lines are outputted 6412 clocks after the positive edge of the 75 Hz signal additional post-processing is done. ...
Page 49
... Connection to a 4-channel DAC Pin Mode = DSD number 117 DSD clock 120 119 left channel 121 right channel S-bus bit stream, generated by the SAA7893HL decimation filter the Serial bit clock frequency output ‘wclk’ DCLK (data bit) frequency frequency 2f 128f s 4f ...
Page 50
... Philips Semiconductors Table 34: Symbol t d(o) 2 11.2.2 I S-PCM generated by the SAA7893HL In Figure 51 generator of the SAA7893HL generates the I pcm_wclk_out t wclk pcm_dclk_out t data pcm_LeRi_out pcm_LsRs_out pcm_CeLf_out 2 Fig 51. Audio I S-bus output timing in Philips format. t wclk t data MSB 2 Fig 52. Audio I S-bus output timing in left justified format. ...
Page 51
... DSD_PCM_9 dsd_left_mix/ i2s_lmrm 119 DSD_PCM_10 dsd_right_mix/ ’0’ 121 DSD_PCM_11 audio clock 29 Rev. 02 — 26 February 2003 SAA7893HL Super audio media player hybrid MCA DAC sdata_ifrf M_x sdata_celfe M_x sdata_Isrs M_x sclk wclk mclk sclk hybrid stereo DAC ...
Page 52
... DSD_PCM_8 120 n.c. DSD_PCM_9 dsd_left_mix 119 DSD_PCM_10 dsd_left dsd_right_mix 121 DSD_PCM_11 dsd_right audio clock 29 Rev. 02 — 26 February 2003 SAA7893HL Super audio media player DSD MCA DAC mclk DSD stereo DAC mclk MCE061 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 53
... DSD_PCM_8 i2s_wclk 120 wclk DSD_PCM_9 i2s_lmrm 119 DSD_PCM_10 sdata_lfrf 121 DSD_PCM_11 n.c. audio clock 29 Rev. 02 — 26 February 2003 SAA7893HL Super audio media player PCM MCA DAC mclk PCM stereo DAC mclk MCE062 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 54
... Product data cmd nop active t addr XX address t dqm upper/lower t data ZZZZ Conditions Rev. 02 — 26 February 2003 SAA7893HL Super audio media player write precharge address XX byte data ZZZZ MBL632 Min Max Unit ...
Page 55
... Conditions D_clk is clock of SDRAM Rev. 02 — 26 February 2003 SAA7893HL Super audio media player nop nop precharge data to SAA7893HL MBL634 Min Max Unit ...
Page 56
... Mbit SDRAM SAA7893HL CKE D_DQ[15:0] DQ(15:0) D_ADDR[11:0] A(11:0) 78 D_ADDR[12] BA0 75 D_ADDR[13] BA1 81 RAS_ D_RASn 82 D_CASn CAS_ 80 WE_ D_Wen 86 D_clk CLK 88 D_UDQM DQMH 89 D_LDQM DQML CS_ Rev. 02 — 26 February 2003 SAA7893HL Super audio media player MCE063 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 57
... V CONVERTOR 100 (LF18CD) 4.7 4.7 100 100 3.3 to 1.8 V CONVERTOR 100 (LF18CD) 4.7 4.7 100 Rev. 02 — 26 February 2003 SAA7893HL Super audio media player SAA7893HL 10 VCC_IO1 nF 4 GND_IO1 37 VCC_IO7 nF 38 GND_IO7 58 VCC_IO2 nF 17 GND_IO2 76 VCC_IO3 nF 69 GND_IO3 92 VCC_IO4 nF 83 GND_IO4 106 ...
Page 58
... Set the DAC PIO pins Set a list of character sets, application can handle Set a list of preferred languages Retrieve information about the album of active disc Retrieve album text items Rev. 02 — 26 February 2003 SAA7893HL Super audio media player © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 59
... Select the front-end interface attached to SA-MP Configure the DAC pins Configure the audio clock for different input stream modes Configure the SDRAM attached to the SAA7893HL Return the pointer to SA-MP interrupt handler Configure the DSD clock polarity Inform SA-MP about the system clock Confi ...
Page 60
... LI I input current on any pin except supplies i(n) 9397 750 10925 Product data Min 0.5 0.5 0.5 0 150 Min 1.65 90 1.65 - 3.0 - 2.0 - VCC_IO - - - - - Rev. 02 — 26 February 2003 SAA7893HL Super audio media player Max Unit 2.1 V 3.8 V 2 125 C 150 C Typ Max Unit 1.8 1.95 V 110 150 mW 1.8 1. ...
Page 61
... scale (1) ( 0.20 20.1 14.1 22.15 16.15 1.0 0.5 0.09 19.9 13.9 21.85 15.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 26 February 2003 SAA7893HL Super audio media player detail (1) ( 0.75 0.81 0.81 0.2 0.12 0.1 ...
Page 62
... The footprint must incorporate solder thieves at the downstream end. 9397 750 10925 Product data Rev. 02 — 26 February 2003 SAA7893HL Super audio media player 2.5mm 3 so called 3 so © ...
Page 63
... Product data Suitability of surface mount IC packages for wave and reflow soldering methods [1] [4] , SO, SOJ Rev. 02 — 26 February 2003 SAA7893HL Super audio media player Soldering method Wave Reflow not suitable suitable [3] not suitable ...
Page 64
... A note is added to 01 20021014 - Product data (9397 750 10341) 9397 750 10925 Product data Figure 44 Section 7.5.1 Section 7.5.2 Section 8.2. Table 11. Rev. 02 — 26 February 2003 SAA7893HL Super audio media player is changed from 100 nF © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 65
... Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation. Rev. 02 — 26 February 2003 SAA7893HL Super audio media player Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 66
... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 February 2003 Document order number: 9397 750 10925 SAA7893HL Super audio media player 12.1 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.2 Reading ...