UDA1355H NXP Semiconductors, UDA1355H Datasheet
UDA1355H
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UDA1355H Summary of contents
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... DATA SHEET UDA1355H Stereo audio codec with SPDIF interface Preliminary specification INTEGRATED CIRCUITS 2003 Apr 10 ...
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... CHARACTERISTICS 16 TIMING CHARACTERISTICS 17 PACKAGE OUTLINE 18 SOLDERING 18.1 Introduction to soldering surface mount packages 18.2 Reflow soldering 18.3 Wave soldering 18.4 Manual soldering 18.5 Suitability of surface mount IC packages for wave and reflow soldering methods 19 DATA SHEET STATUS 20 DEFINITIONS 21 DISCLAIMERS 22 PURCHASE OF PHILIPS I 2 Preliminary specification UDA1355H 2 C COMPONENTS ...
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... DAC digital sound processing Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio sampling frequencies Automatic de-emphasis when using IEC 60958 to DAC Soft mute made of a cosine roll-off circuit selectable via pin MUTE or L3-bus interface 3 Preliminary specification UDA1355H made of a cascade of three s ...
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... By default the DAC output and the digital data interface output are muted when the decoder is not in lock. The UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock- incoming SPDIF or digital audio signal, and in the mean ...
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... IEC 60958 input; code = 0; A-weighted kHz kHz s 5 Preliminary specification MIN. TYP. 2.7 3.0 2.7 3.0 2.7 3.0 2.7 3.0 2.7 3.0 4.7 4.7 1.7 1.7 10.2 10.4 0.2 0.2 0.9 1.2 18.2 34.7 0.5 0.7 40 900 0 kHz kHz 100 UDA1355H MAX. UNIT 3.6 V 3.6 V 3.6 V 3 ...
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... A-weighted code = 0; A-weighted kHz kHz s IEC 60958 input; f DAC in playback mode DAC in Power-down mode 6 Preliminary specification MIN. TYP. 1.0 0 100 12.288 10 250 = 48 kHz UDA1355H MAX. UNIT MHz ...
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... V DDE TIMING AUDIO AUDIO INTER- FEATURE FEATURE POLATOR PROCESSOR PROCESSOR INPUT AND OUTPUT SELECT DATA OUT IEC 60958 ENCODER UDA1355H CONTROL INTERFACE MODE0 MODE2 V SSE MP2 SEL_STATIC MODE1 Fig.1 Block diagram. V DDA1 39 40 VOUTL DAC NOISE ...
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... SFOR1 for static mode, SCL for I L3CLOCK for L3-bus mode multi-purpose pin 2: SFOR0 for static mode, SDA for I L3DATA for L3-bus mode positive ADC reference voltage negative ADC reference voltage 8 Preliminary specification UDA1355H DESCRIPTION s 2 C-bus mode or L3-bus mode 2 C-bus mode and 2 ...
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... ADC supply voltage reference voltage for ADC and DAC DAC supply voltage DAC left channel output DAC ground DAC right channel output test control input DAC mute input DESCRIPTION 2 C-bus specification with open drain tolerant 9 Preliminary specification UDA1355H DESCRIPTION ...
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... BCKO CLK_OUT 7 FUNCTIONAL DESCRIPTION 7.1 IC control The UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the 2 I C-bus with a clock up to 400 kHz or the L3-bus with a clock MHz recommended to use the microcontroller interface since this gives full access to all the IC features ...
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... Two times 40 bits of channels status bits of the SPDIF input signal. 7.3 Clock systems The UDA1355H has two clock systems. The first system uses an external crystal of 12.288 MHz to generate the audio related system clocks. Only a crystal with a frequency of 12.288 MHz is allowed. The second system is a PLL which locks on the SPDIF or incoming digital audio signal (e ...
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... PLL, depending on the selected application and control mode. 7.4 UDA1355H The UDA1355H IEC 60958 decoder can select one of four SPDIF input channels. An on-chip amplifier with hysteresis MGU830 amplifies the SPDIF input signal to CMOS level, making it possible to accept both analog and digital SPDIF signals (see Fig ...
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... In the UDA1355H, digital data is detected via bit PCM, or via the sync bytes as specified by IEC. These sync bytes are two sync words, F872H and 4E1FH (two subframes) preceded by four or more subframes filled with zeros ...
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... V (RMS) volume controls with a range from + (RMS) and 1 V (RMS) linear mute that can be used to prevent plops when 0.5 V (RMS) powering-up or powering down the ADC front path. 14 Preliminary specification UDA1355H MODE [ 3 SPDIF OUT MODE [ 2:0 ] SEL_STATIC MGU833 D ECIMATION ...
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... Hz 44.1 kHz gain range with steps = 300 Hz 44.1 kHz gain range with steps. ), positive or negative peak gain and shape factor (see s UDA1355H dB; hold for ...
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... The digital mixer can be used as a cross over or a selector. A functional block diagram of the mixer mode is shown in Fig.9. This mixer can be used in microcontroller mode only. The UDA1355H can be set to the mixer mode by setting bit MIX = 1. In the mixer mode, there are three volume and 10 handbook, halfpage ...
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... MUTE channel 1 7.7.4 D IGITAL SILENCE DETECTOR The UDA1355H is equipped with a digital silence detector. This detects whether a certain amount of consecutive samples are 0. The number of samples can be set with bits SD_VALUE[1:0] to 3200, 4800, 9600 or 19600 samples. The digital silence detection status can be read via the microcontroller interface ...
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... LSB-justified; 24 bits MSB-justified. 7.9 Power-on reset The UDA1355H has a dedicated reset pin with an internal pull-down resistor. In this way a Power-on reset circuit can be made with a capacitor and a resistor at pin RESET. The external resistor is needed since the pad tolerant. This means that there is a transmission gate in series with the input and the resistor inside the pad cannot be seen from the outside world (see Fig ...
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... The UDA1355H can be controlled by static pins, the L3-bus the pin count, only basic functions are available in static mode. For optimum use of the UDA1355H features, the microcontroller mode is strongly recommended. There are 11 application modes available in the static MGU835 mode and 14 application modes in microcontroller mode ...
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... PLL PLL xtal xtal xtal xtal xtal xtal xtal xtal PLL PLL xtal PLL xtal PLL PLL xtal xtal PLL xtal not used UDA1355H PLL LOCKS 2 S-BUS ON INPUT PLL SPDIF 2 I S-bus PLL SPDIF xtal xtal xtal 2 xtal I S-bus xtal SPDIF ...
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... DAC sound features can be used – SPDIF output channel status bits (two times 40 bits) setting. 2003 Apr SPDIF slave I S INPUT 21 Preliminary specification UDA1355H SCHEMATIC SPDIF LOCK PLL MUTE DAC SPDIFOUT OUTPUT I S master MGU836 2 ...
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... I S slave I S master EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU838 XTAL SPDIF OUT OUTPUT XTAL DAC SPDIF OUT INPUT I S OUTPUT slave I EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU840 UDA1355H MUTE SPDIFOUT master MGU839 MUTE 2 S master ...
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... SPDIF OUT INPUT I S OUTPUT slave I EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) MGU841 LOCK XTAL PLL ADC SPDIF OUT INPUT I S OUTPUT slave EXTERNAL DSP (SAA7715) MGU842 UDA1355H MUTE 2 S master MUTE DAC master ...
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... SPDIF output channel status bits (two times 40 bits) setting. 2003 Apr XTAL S ADC 2 S ADC INPUT 24 Preliminary specification UDA1355H SCHEMATIC SPDIF LOCK PLL DAC SPDIF OUT SPDIF OUTPUT MGU843 LOCK XTAL PLL DAC SPDIF OUT 2 ...
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... See microcontroller mode 13 See microcontroller mode 14 See microcontroller mode 15 Not used 2003 Apr and DAC; 25 Preliminary specification UDA1355H SCHEMATIC SPDIF LOCK XTAL PLL DAC SPDIF IN SPDIF OUT INPUT OUTPUT slave I S master EXTERNAL DSP (e ...
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... S-bus data preamble detected 2 HIGH I S-bus data preamble detected L3MODE for L3-bus mode; no function for I L3CLOCK for L3-bus mode or SCL for I L3DATA for L3-bus mode or SDA for I LOW no mute HIGH mute active 26 Preliminary specification UDA1355H DESCRIPTION 2 C-bus 2 C-bus mode 2 C-bus mode ...
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... PLL xtal xtal xtal xtal PLL xtal xtal PLL xtal PLL PLL xtal xtal PLL PLL xtal PLL PLL 27 Preliminary specification UDA1355H ( S-BUS I S-BUS DAC INPUT OUTPUT SLAVE MASTER PLL - PLL PLL PLL PLL PLL PLL xtal ...
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... I S slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) XTAL ADC INPUT slave EXTERNAL DSP (e.g. equalizing, spatializing) (SAA7715) 28 Preliminary specification UDA1355H SPDIF LOCK MUTE DAC SPDIF OUT S OUTPUT master MGU847 MUTE DAC SPDIF OUT OUTPUT master MGU848 ...
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... Possibility to process inputs ADC or 2 SPDIF, via I S-bus using an external DSP and then to output SPDIF. 11 Not used 2003 Apr with BCK ADC ADC 29 Preliminary specification UDA1355H SCHEMATIC SPDIF LOCK XTAL PLL DAC SPDIF IN SPDIF OUT INPUT I S OUTPUT 2 2 ...
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... SPDIF LOCK XTAL PLL ADC SPDIF IN SPDIF OUT OUTPUT INPUT LOCK PLL ADC SPDIF OUT INPUT I S OUTPUT UDA1355H MUTE DAC master MGU851 MUTE DAC SPDIF OUT master MGU852 MUTE DAC master MGU853 ...
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... W channel 2 M channel 1 sub-frame sub-frame frame 0 Fig.12 SPDIF signal format audio sample word B Fig.13 Sub-frame format 31 Preliminary specification UDA1355H SPDIF hierarchical layers channel 2 M channel 1 W frame 191 block validity flag user data channel status ...
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... Level III, variable pitch shifted clock mode: A deviation of 12.5% of the nominal sampling frequency is possible. The UDA1355H inputs support level I, II, and III as specified by the IEC 60958 standard. 9.3.2 R ISE AND FALL TIMES Rise and fall times (see Fig.14) are defined as: ...
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... The device address of the UDA1355H is given in Table 17, being the first 6 bits of the device address byte. The address can be set one of two by using pin MODE1 (pin A0 in microcontroller mode). Table 17 L3-bus device address MSB ...
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Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 DOM bits ...
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... I C-bus according the Philips specification. data line change stable; of data data valid allowed Fig.17 Bit transfer on the I 35 Preliminary specification UDA1355H D14 D13 D12 ...
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... The device address can be one of two, being set by bit A0 which corresponds to pin MODE1. The UDA1355H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. ...
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... The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1355H. Table 22 Master transmitter writes to the UDA1355H registers in the I DEVICE REGISTER R/W ADDRESS ADDRESS ...
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... Then the microcontroller generates the device address 0011010 again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge (A) follows from the UDA1355H. 8. The UDA1355H sends two bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledged follows from the microcontroller. ...
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... Philips Semiconductors Stereo audio codec with SPDIF interface 12 REGISTER MAPPING In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the mapping of the readable and writable registers is given. The explanation of the register definitions are explained in Sections 12.2 and 12.3. 12.1 Address mapping ...
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... BIT 7 6 Symbol MODE3 MODE2 Default 0 0 2003 Apr 10 DESCRIPTION PON_XTAL XTL_DIV4 XTL_DIV3 PLL MODE1 MODE0 ws_detct_EN ws_detct_set CLKOUT_ Preliminary specification UDA1355H 10 9 XTL_DIV2 XTL_DIV1 SEL1 XTL_DIV0 0 0 CLKOUT_ SEL0 0 ...
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... Table 26 Description of register bits (address 00H) BIT SYMBOL 15 EXPU EXPU. Bit EXPU is reserved for manufacturers evaluation and should be kept untouched for normal operation of UDA1355H. 14 reserved 13 PON_XTALPLL Power control crystal oscillator and PLL. If this bit is logic 0, then the crystal oscillator and PLL are turned off; if this bit is logic 1, then the crystal oscillator and PLL are running ...
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... DIGOUT1 DIGOUT0 Preliminary specification UDA1355H XTL_DIV0 OUTPUT RATE 0 256 24 kHz 1 384 24 kHz 0 256 48 kHz 1 384 48 kHz 0 256 96 kHz 1 384 96 kHz MODE0 FUNCTION 0 mode 0 1 mode 1 0 mode 2 ...
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... The registers have their own clock, which means that there cannot be a dead-lock situation reserved 2003 Apr 10 DESCRIPTION 2 S-bus DESCRIPTION 43 Preliminary specification UDA1355H SFORI2 SFORI1 SFORI0 ...
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... Interpolator clock enable. If this bit is logic 0, then the clock to interpolator and FSDAC is disabled; if this bit is logic 1, then the clock to the interpolator and FSDAC is running. 2003 Apr 10 DESCRIPTION 2 S-bus Preliminary specification PON_ADCL PON_ADCR PON_ADC_bias EN_DEC DESCRIPTION UDA1355H EN_INT 1 ...
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... Preliminary specification UDA1355H DESCRIPTION 10 9 MVCL_2 MVCL_1 MVCR_2 MVCR_1 (see Table 38). dB (see Table 38). MVCL_1 MVCL_0 VOLUME (dB) MVCR_1 MVCR_0 0. 0 ...
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... Preliminary specification UDA1355H MVCL_1 MVCL_0 MVCR_1 MVCR_0 VC2_3 VC2_2 VC2_1 ...
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... M0 TRL1 TRL0 TRR1 TRR0 Preliminary specification VC2_0 VOLUME (dB) VC1_0 BBL3 BBL2 BBL1 BBR3 BBR2 BBR1 0 0 DESCRIPTION UDA1355H 9 8 BBL0 BBR0 0 0 ...
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... Preliminary specification DESCRIPTION MIN. SET (dB FLAT SET (dB) MIN SET (dB) MAX SET (dB UDA1355H MAX. SET (dB ...
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... MIXGAIN WS_SEL DE_SW (1) MIX ( Preliminary specification 11 10 MT2 DE2_2 DE2_1 MT1 DE1_2 DE1_1 0 0 DESCRIPTION MIX_GAIN DAC GAIN (dB) ( UDA1355H 9 8 DE2_0 DE1_0 ...
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... DAC channel 2 input selection. Value to select the input mode to channel 2 of the interpolator (see Table 54). DAC channel 1 input selection. Value to select the input mode to channel 1 of the interpolator (see Table 54). 50 Preliminary specification UDA1355H MIXER OUTPUT GAIN FUNCTION off 32 kHz 44.1 kHz ...
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... Preliminary specification UDA1355H DESCRIPTION FUNCTION dB ...
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... BASS_x_5 BASS_x_4 BASS_x_3 0 0 DESCRIPTION 13 12 MA_ MA_ MA_ DECL5 DECL4 DECL3 MA_ MA_ MA_ DECR5 DECR4 DECR3 Preliminary specification UDA1355H BASS_x_2 BASS_x_1 BASS_x_0 MA_ MA_ DECL2 DECL1 ...
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... PGA_GAIN_ PGA_GAIN_ CTRLL2 CTRLL1 PGA_GAIN_ PGA_GAIN_ CTRLR2 CTRLR1 UDA1355H MA_ GAIN (dB) MA_ 0 +24.0 1 +23.5 0 +23 +1 62.0 1 62.5 0 63 PGA_GAIN_ CTRLL0 0 0 PGA_GAIN_ CTRLR0 0 ...
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... CTRLL1 PGA_GAIN_ CTRLR1 ADCPOL_INV DESCRIPTION 54 Preliminary specification UDA1355H DESCRIPTION PGA_GAIN_ CTRLL0 GAIN (dB) PGA_GAIN_ CTRLR0 DC_SKIP ...
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... PON_SPDI IEC 60958 input from pin SPDIF0 01 = IEC 60958 input from pin SPDIF1 10 = IEC 60958 input from pin SPDIF2 11 = IEC 60958 input from pin SPDIF3 55 Preliminary specification DESCRIPTION SLICER_SEL1 0 0 DESCRIPTION UDA1355H SLICER_SEL0 0 ...
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... ADC 2 001 = I S-bus input 010 = not used 011 = interpolator mix output 100 = SPDIF0 loop through 101 = SPDIF1 loop through 110 = SPDIF2 loop through 111 = SPDIF3 loop through 56 Preliminary specification UDA1355H DESCRIPTION 8 SPDO_ VALID ...
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... Audio sample word length. Value to signal the maximum audio sample word length. If bit 32 is logic 0, then the maximum length is 20 bits; if bit 32 is logic 1, then the maximum length is 24 bits (see Table 73). reserved 57 Preliminary specification UDA1355H SPDO_ SPDO_ SPDO_ ...
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... Channel status. Value indicating the consumer use of the status block. This bit is logic 0. SPDO_BIT34 Preliminary specification UDA1355H DESCRIPTION SPDO_BIT33 WORD LENGTH 0 not indicated 1 16 bits 0 18 bits 1 reserved 0 19 bits ...
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... Preliminary specification UDA1355H WORD LENGTH indicated 20 bits 22 bits reserved 23 bits 24 bits 21 bits reserved CHANNEL NUMBER don’t care A (left for stereo transmission) B (right for stereo transmission ...
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... Cp- and L-bit status solid state memory based products experimental products not for commercial sale reserved reserved, except 000 0000 and 000 0001L Preliminary specification UDA1355H SOURCE NUMBER FUNCTION ...
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... Mute status channel 1. If this bit is logic 0 then the interpolator channel 1 is not muted; if this bit is logic 1 then the interpolator channel 1 is muted DESCRIPTION 61 Preliminary specification DESCRIPTION MT_ADC_stat UDA1355H 8 0 OVERFLOW ...
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... Preliminary specification B_ERR DESCRIPTION SPDI_ SPDI_ SPDI_ BIT35 BIT34 BIT33 11 10 SPDI_ SPDI_ SPDI_ BIT27 BIT26 BIT25 3 2 SPDI_ SPDI_ SPDI_ BIT19 BIT18 BIT17 UDA1355H 8 SPDO_STATUS 0 SPDIF_LOCK SPDI_ BIT32 9 8 SPDI_ BIT24 1 0 SPDI_ BIT16 ...
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... SPDI_ SPDI_ BIT11 BIT10 BIT9 3 2 SPDI_ SPDI_ SPDI_ BIT3 BIT2 BIT1 MIN. 2 3000 250 = 3 note 4 DD SSA1 DDA1 CONDITIONS VALUE 70 UDA1355H 9 8 SPDI_ BIT8 1 0 SPDI_ BIT0 MAX. UNIT 5.0 V +125 C +85 C +3000 V +250 V 100 100 mA UNIT ...
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... 0.85V 0.9V 0. Preliminary specification UDA1355H MIN. TYP. MAX. 3.0 3.6 V 3.0 3.6 V 3.0 3.6 V 3.0 3.6 V 3.0 3.6 V 4.7 mA 4.7 mA 1.7 1.7 10.2 mA 10.4 mA 0.2 0.2 0.9 mA 1 ...
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... 1.16 dBFS digital o output kHz dB; A-weighted kHz dB; A-weighted code = 0; A-weighted kHz kHz s 65 Preliminary specification UDA1355H MIN. TYP. MAX. 0.5V 0.55V 900 mV 0 ...
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... DAC in Power-down mode ) must be connected to the same external power supply unit unless otherwise specified. L CONDITIONS kHz 44.1 kHz kHz kHz s 66 Preliminary specification UDA1355H MIN. TYP. MAX. 0.2 0.5 3 tbf 74 63 must be used in MIN. TYP. MAX. UNIT 250 85.0 63.0 60.0 40 ...
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... STOP and START 1.3 condition 100 67 Preliminary specification UDA1355H MIN. TYP. MAX. UNIT 10 ns 400 kHz s s 300 ns b ...
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... WS t BCKH t r BCK T cy(BCK) DATAO DATAI 2003 Apr 10 CONDITIONS note 5 for each bus line t h(WS su(WS) t BCKL t d(DATAO-WS) 2 Fig.20 I S-bus interface timing. 68 Preliminary specification UDA1355H MIN. TYP. MAX. UNIT 400 1 cycle. 64fs t d(DATAO-BCK) t h(DATAO) t su(DATAI) t h(DATAI) MGS756 ...
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... Fig.22 L3-bus interface timing for data transfer mode (write and read). 2003 Apr 10 t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.21 L3-bus interface timing for address mode. t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 t d(L3)R 69 Preliminary specification UDA1355H t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 t h(L3)D BIT 7 t dis(L3)R MBL566 ...
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Acrobat reader. white to force landscape pages to be ... SDA t BUF t LOW t r SCL t HD;STA t HD;DAT P S ...
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... 2.5 scale (1) ( 0.4 0.25 10.1 10.1 12.9 0.8 0.2 0.14 9.9 9.9 12.3 REFERENCES JEDEC JEITA 71 Preliminary specification detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION UDA1355H SOT307 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 97-08-01 03-02-25 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 72 Preliminary specification UDA1355H ...
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... Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 Apr 10 (1) not suitable not suitable suitable not recommended not recommended 73 Preliminary specification UDA1355H SOLDERING METHOD (2) WAVE REFLOW suitable (3) suitable suitable (4)(5) suitable ...
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... Preliminary specification UDA1355H DEFINITION These products are not Philips Semiconductors ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 2003 Apr 10 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 75 Preliminary specification UDA1355H 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited ...