ISP1501BE NXP Semiconductors, ISP1501BE Datasheet
ISP1501BE
Related parts for ISP1501BE
ISP1501BE Summary of contents
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ISP1501 Hi-Speed Universal Serial Bus peripheral transceiver Rev. 02 — 21 November 2002 1. General description The ISP1501 is a full-function transceiver designed to provide a Hi-Speed Universal Serial Bus (USB) analog front-end to Application-Specific Integrated Circuits (ASICs) and Field ...
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... Digital still camera Printer, e.g. External storage device, e.g. 4. Ordering information Table 1: Ordering information Type number Package Name Description ISP1501BE LQFP48 plastic low profile quad flat package; 48 leads; body 7 9397 750 10025 Product data Color printer Multi-functional printer Portable hard disk ® Zip drive ® ...
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Philips Semiconductors 5. Block diagram CLKOUT48 CLKOUT30 2 MODE0, MODE1 RESET SUSPEND TX_VALID/OE TX_READY TX_BS_EN/FSE0 TX_LAST_BYTE DDIR 16 DATA15 to DATA0 RX_VALID/VP RX_INACTIVE/VM RX_BS_ERROR/RCV RX_LAST_BYTE TEST_J_K/ CCA1 to V CCA3 2 V CCD1 , V CCD2 2 DGND1, ...
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... Symbol SUSPEND TX_VALID/ OE RESET AGND1 V CCA1 DM 9397 750 10025 Product data SUSPEND 1 2 TX_VALID/OE RESET 3 AGND1 4 V CCA1 ISP1501BE CCA2 8 RPU 9 AGND2 10 MODE0 11 MODE1 12 Pin description [1] Pin Type Description 1 I enables power saving mode for USB suspend state 2 I pin function depends on operating mode (see State = 0, 1 — ...
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Philips Semiconductors Table 2: Symbol DP V CCA2 RPU AGND2 MODE0 MODE1 CLKOUT48 RREF CLKOUT30 V CCA3 XTAL2 XTAL1 AGND3 DDIR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 V CCD1 DGND1 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ...
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Philips Semiconductors Table 2: Symbol DGND2 TX_LAST_BYTE TX_READY TX_BS_EN/FSE0 44 TEST_J_K/ VO RX_BS_ERROR/ RCV RX_INACTIVE/ VM RX_VALID/ VP [1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals. [2] FS: full-speed (Original USB); HS: high-speed (Hi-Speed USB). 9397 ...
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Philips Semiconductors 7. Functional description The ISP1501 supports both full-speed (FS) and high-speed (HS) USB physical layer for a Hi-Speed USB peripheral. An adaptive termination circuit ensures a correct 45 Calibration is done at power-on and after any operating state ...
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Philips Semiconductors intended states without slew-rate control. This is permitted because driving during suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to the ‘K’ state) for a period ...
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Philips Semiconductors When TEST_J_K is set to logic 1, the sampled data from the differential amplifier will not be NRZI decoded and bit de-stuffed. All serial HS USB signals are passed-through and converted to 16-bit data on the parallel data ...
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Philips Semiconductors Table 3: MODE[1:0] 8.2 State transitions A Hi-Speed USB peripheral handles more than one electrical state under the USB specification. The ISP1501 accommodates the various states through the MODE[1:0] input pins. Table 4: State ...
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Philips Semiconductors 8.2.2 Full-speed (FS) state In the full-speed (FS) state (MODE[1:0] = 01), an external pull-up resistor of 1.5 k RPU resistor is internally connected to the DP line. The FS transceiver is enabled, and the legacy (Original USB) ...
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Philips Semiconductors Fig 6. High-speed chirp state. 8.3 Reset The output clocks are affected by pin RESET and may show a momentary change at RESET. The ASIC may not transmit or receive data while the ISP1510 RESET is driven LOW. ...
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Philips Semiconductors 9. Full-speed functionality (1) Connected in FS state and HS chirp state. Fig 7. Full-speed transceiver functional diagram Table logic 0 FSE0 Table logic 1 Differential input [1] ...
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Philips Semiconductors 10. High-speed functionality 1 SUSPEND 45 TEST_J_K 46 RX_BS_ERROR 47 RX_INACTIVE 48 MUX RX_VALID 39 RX_LAST_BYTE 12 MODE1 20 DDIR DATA15 to DATA0 shift enable 43 TX_READY 2 TX_VALID 42 TX_LAST_BYTE ...
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Philips Semiconductors Table 7: TX_LAST_BYTE TX_LAST_BYTE (1) TX_READY is only de-asserted during a transmission if the internal FIFO is full. Fig 9. HS transmit; single-byte EOP ending on 16-bit boundary. TX_LAST_BYTE (1) TX_READY is only de-asserted during a transmission if ...
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Philips Semiconductors CLKOUT30 TX_READY TX_LAST_BYTE TX_BS_EN SYNC DATA [ 15:8 ] 00H DATA [ 7:0 ] 00H TX_VALID (1) TX_READY is only de-asserted during a transmission if the internal FIFO is full. Fig 11. HS transmit; 5-byte EOP ending on ...
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Philips Semiconductors Table 8: RX_LAST_BYTE [1] This condition is only valid in the cycle immediately after pin RX_VALID goes LOW. Fig 13. HS receive timing; single-byte EOP starting on the high byte. Fig 14. HS receive timing; single-byte EOP starting ...
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Philips Semiconductors CLKOUT30 RX_LAST_BYTE RX_BS_ERROR DATA [ 15:8 ] DATA [ 7:0 ] RX_VALID Fig 15. HS receive timing; 5-bytes EOP starting on the low byte. CLKOUT30 TX_READY TX_LAST_BYTE TX_BS_EN SYNC DATA [ 15:8 ] 00H DATA [ 7:0 ] ...
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Philips Semiconductors handbook, full pagewidth CLKOUT30 HIGH TX_READY TX_VALID DATA [ 15:0 ] 0000H DP/DM (1) Time interval controlled by the SIE. Fig 17. HS chirp transmit timing. For HS chirp reception, the 16-bit data bus is in the bypass ...
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Philips Semiconductors handbook, full pagewidth 480 MHz clock CLKOUT30 DATA [ 15:0 ] TX_READY 8 HS bit times TX_VALID driver enabled DP/DM Fig 19. HS transmit path delay. 10.5 High-speed receive path delay In the HS receive mode, the SYNC ...
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Philips Semiconductors 11. Clocking The CLKOUT30 and CLKOUT48 pins are free running clocks at 30 MHz and 48 MHz, respectively. 11.1 Power-up behavior Both output clocks (CLKOUT30 and CLKOUT48) are held LOW (logic 0) at power-up for a period of ...
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Philips Semiconductors 12. Termination calibration The on-chip termination is calibrated after power-up and mode change to provide 45 during calibration. 12.1 Power-up behavior This internal termination calibration occurs 21600 oscillator cycles after power-up. Similar to the clock blocking mechanism, the ...
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Philips Semiconductors 13. Limiting values Table 9: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V analog supply voltage CCA V digital supply voltage CCD V input voltage I I latch-up current lu ...
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Philips Semiconductors Table 12: Static characteristics: digital pins 3 CCA CCD AGND Symbol Parameter Input levels V LOW-level input voltage IL V HIGH-level input voltage IH Output levels V LOW-level ...
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Philips Semiconductors Table 13: Static characteristics: analog I/O pins DP and DM 3 CCA CCD AGND Symbol Parameter V high-speed HIGH-level output HSOH voltage (differential) V chirp-J output voltage (differential) ...
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Philips Semiconductors Table 14: Dynamic characteristics: analog I/O pins (DP/DM 3 CCA CCD AGND Symbol Parameter t driver disable delay PHZ (OE to DP, DM) t PLZ t driver enable ...
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Philips Semiconductors 16.1 High-speed signals High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4 test points have been defined (see Specification Rev. 2.0 defines the eye patterns in several ‘templates’. For ISP1501 only Templates 1 ...
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Philips Semiconductors Table 15: Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 [1] In the unit interval following a transition. [2] In all other cases. 16.1.2 Template 4 (receive waveform) The ...
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Philips Semiconductors Table 16: Name Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 17. Parallel digital interface timing 17.1 High-speed transmit timing CLKOUT30 DATA [ 15:0 ] TX_VALID TX_LAST _BYTE TX_BS_EN TX_READY ...
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Philips Semiconductors Table 17: High-speed transmit timing CLKOUT30 duty cycle = 50%; see Figure Symbol Parameter t data set-up time to rising su3(HSTX) clock edge t data hold time after rising h3(HSTX) clock edge t TX_VALID set-up time to su0(HSTX) ...
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Philips Semiconductors Table 18: High-speed receive timing CLKOUT30 duty cycle = 50%; see Figure Symbol Parameter t received data output delay d0(HSRX) after falling clock edge t RX_VALID delay after falling d1(HSRX) clock edge t RX_LAST_BYTE delay after d2(HSRX) falling ...
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Philips Semiconductors 19. Test information (1) Internally connected to pin DP; FS operating state (see (2) C Fig 31. FS test circuit. Fig 32. Load for VM, VP and RCV in FS mode. (1) Transmitter: connected to 50 (2) Receiver: ...
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Philips Semiconductors 20. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the ...
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Philips Semiconductors 21. Soldering 21.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...
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Philips Semiconductors During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. ...
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Philips Semiconductors 22. Revision history Table 20: Revision history Rev Date CPCN Description 02 20021121 Product data (9397 750 10025); supersedes Objective specification of ISP1501-01 of July 14th, 2000. Modifications: • Globally changed USB 2.0 and USB 1.1 to Hi-Speed ...
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Philips Semiconductors Table 20: Revision history …continued Rev Date CPCN Description 02 20021121 Product data (9397 750 10025); supersedes Objective specification of ISP1501-01 of July 14th, 2000. Modifications (continued): • Made the following changes in – Corrected typo for pin ...
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Philips Semiconductors Table 20: Revision history …continued Rev Date CPCN Description 02 20021121 Product data (9397 750 10025); supersedes Objective specification of ISP1501-01 of July 14th, 2000. Modifications (continued): • Added • In • In • In • In • ...
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Philips Semiconductors 23. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...
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Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . ...