P89C51RD NXP Semiconductors, P89C51RD Datasheet
P89C51RD
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P89C51RD Summary of contents
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... P89C51RC+/P89C51RD+ 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM Product specification Replaces 89C51RC+/RD+ of 1999 Apr 01 (see Notes 1 and 2 on page 2) Supersedes data of 1999 Apr 01 IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 1999 Oct 27 ...
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... P89C51RD+IA P89C51RC+IB P89C51RD+IB P89C51RC+JN P89C51RD+JN P89C51RC+JA P89C51RD+JA P89C51RC+JB P89C51RD+JB NOTE: 1. SOT not assigned for this package outline. 1999 Oct 27 FEATURES 80C51 Central Processing Unit On-chip FLASH Program Memory with In-System Programming (ISP) capability Boot ROM contains low level FLASH programming routines and a ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM ORDERING INFORMATION DEVICE NUMBER (P89C51RC+) P89C51RC+ (FLASH) P89C51RD+ (FLASH) BLOCK DIAGRAM RAM ADDR RAM REGISTER B ACC REGISTER PSEN ALE TIMING AND EAV CONTROL PP RST PD OSCILLATOR ...
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... CC PP Pin Function 1 P1.5/CEX2 2 P1.6/CEX3 3 P1.7/CEX4 4 RST 5 P3.0/RxD 6 NIC* 7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD 14 XTAL2 15 XTAL1 * NO INTERNAL CONNECTION 4 Product specification P89C51RC+/P89C51RD LCC Pin Function Pin Function 16 P3.4/T0 31 P2.7/A15 32 PSEN 17 P3.5/T1 33 ALE 18 P3.6/WR 34 NIC* 19 P3.7/RD 20 XTAL2 35 EA ...
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... O 1999 Oct 27 P89C51RC+/P89C51RD+ Ground reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory ...
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... To avoid “latch-up” effect at power-on, the voltage on any pin (other than V respectively. 1999 Oct 27 P89C51RC+/P89C51RD+ Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...
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... SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. 1. Reset value depends on reset source. 2. The state of the ENBOOT bit depends on the status byte and PSEN when reset is exited. See the AUXR1 description on page 20. 1999 Oct 27 P89C51RC+/P89C51RD+ BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB E7 E6 ...
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... However, minimum and maximum high and low times specified in the data sheet must be observed. 1999 Oct 27 P89C51RC+/P89C51RD+ BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB D7 D6 ...
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... Power-down Internal Power-down External 1999 Oct 27 P89C51RC+/P89C51RD+ Design Consideration When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited ...
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... EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Figure 1. Timer/Counter 2 (T2CON) Control Register 1999 Oct 27 P89C51RC+/P89C51RD+ Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. ...
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... Baud rate generator 0 (off) TL2 TH2 (8-bits) (8-bits) Control TR2 Capture RCAP2L RCAP2H Control Figure 2. Timer 2 in Capture Mode — — — — Product specification P89C51RC+/P89C51RD+ MODE TF2 Timer 2 Interrupt EXF2 SU00066 Reset Value = XXXX XX00B T2OE DCEN 1 0 SU00729 ...
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... CONTROL (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 CONTROL RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 12 Product specification P89C51RC+/P89C51RD+ TF2 TIMER 2 INTERRUPT EXF2 SU00067 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION DOWN T2EX PIN ...
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... EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. 13 Product specification P89C51RC+/P89C51RD+ Timer 1 Overflow 2 “0” “1” ...
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... NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 1999 Oct 27 P89C51RC+/P89C51RD+ If Timer 2 is being clocked internally , the baud rate is: f OSC Baud Rate + [65536 * (RCAP2H, RCAP2L)]] ...
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... Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 1999 Oct 27 P89C51RC+/P89C51RD+ Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires bit 0 and it ignores bit 1 ...
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... REN TB8 RB8 Description Baud Rate** shift register f /12 OSC 8-bit UART variable 9-bit UART f / /32 OSC OSC 9-bit UART variable Figure 7. SCON: Serial Port Control Register 16 Product specification P89C51RC+/P89C51RD+ Reset Value = 0000 0000B SU00043 ...
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... POF GF1 GF0 Figure 8. UART Framing Error Detection SM0 SM1 SM2 REN COMPARATOR 17 Product specification P89C51RC+/P89C51RD ONLY IN STOP MODE 2, 3 BIT SCON TI RI (98H) PCON PD IDL (87H) SU01191 D7 D8 SCON TB8 RB8 TI RI ...
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... REQUEST BITS HARDWARE CLEAR? IE0 TP0 IE1 TF1 CF, CCFn n = 0–4 RI, TI TF2, EXF2 ET2 ES ET1 EX1 Figure 10. IE Registers 18 Product specification P89C51RC+/P89C51RD+ VECTOR ADDRESS (L) Y (T) 03H Y 0BH N (L) Y (T) 13H Y 1BH N 33H N 23H N 2BH 1 0 ET0 ...
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... Timer 0 interrupt priority bit high. IPH.0 PX0H External interrupt 0 priority bit high. 1999 Oct PT2 PS PT1 PX1 Figure 11. IP Registers PT2H PSH PT1H PX1H Figure 12. IPH Registers 19 Product specification P89C51RC+/P89C51RD PT0 PX0 SU01038 1 0 PT0H PX0H SU01039 ...
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... MOVX @ DPTR , A 1 JMP @ A + DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. 20 Product specification P89C51RC+/P89C51RD+ DPTR1 DPTR0 DPH DPL (83H) (82H) EXTERNAL ...
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... When a module is used in the PWM mode these registers are used to control the duty cycle of the output. 16 BITS MODULE 0 MODULE 1 MODULE 2 MODULE 3 MODULE 4 Figure 14. Programmable Counter Array (PCA) 21 Product specification P89C51RC+/P89C51RD+ P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 SU00032 ...
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... CF CR –– CCF4 CCF3 Figure 15. PCA Timer/Counter CF CR –– CCF4 CCF3 CCAPMn.0 ECCFn Figure 16. PCA Interrupt System 22 Product specification P89C51RC+/P89C51RD+ TO PCA MODULES OVERFLOW INTERRUPT CL CMOD CPS1 CPS0 ECF (D9H) CCON CCF2 CCF1 CCF0 (D8H) SU00033 CCON ...
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... External clock at ECI/P1.2 pin (max. rate = f Figure 17. CMOD: PCA Counter Mode Register – CCF4 CCF3 CCF2 Figure 18. CCON: PCA Counter Control Register 23 Product specification P89C51RC+/P89C51RD+ Reset Value = 00XX X000B CPS0 ECF OSC SU00035 Reset Value = 00X0 0000B CCF1 CCF0 1 ...
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... CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. 24 Product specification P89C51RC+/P89C51RD+ Reset Value = X000 0000B PWMn ECCFn 1 0 ...
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... CCF3 CCF2 CCAPnL (TO CCFn) MATCH CL ECOMn CAPPn CAPNn MATn TOGn Figure 22. PCA Compare Mode 25 Product specification P89C51RC+/P89C51RD+ CCON CCF0 (D8H) PCA INTERRUPT PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CCAPMn ECCFn (DAH – DEH) SU00749 CCON CCF1 CCF0 (D8H) ...
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... ENABLE 8–BIT COMPARATOR CL >= CCAPnL CL OVERFLOW PCA TIMER/COUNTER CAPPn CAPNn MATn TOGn PWMn Figure 24. PCA PWM Mode 26 Product specification P89C51RC+/P89C51RD+ CCON CCF1 CCF0 (D8H) PCA INTERRUPT TOGGLE CEXn CCAPMn, n: 0..4 PWMn ECCFn (DAH – DEH SU00751 0 CEXn 1 CCAPMn, n: 0..4 ECCFn (DAH – ...
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... Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 16 2 count of the PCA timer. 27 Product specification P89C51RC+/P89C51RD+ CMOD CPS1 CPS0 ECF (D9H) RESET CCAPM4 ...
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... Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H 255 counts of the current PCA SETB EA ; timer value RET Figure 26. PCA Watchdog Timer Initialization Code 1999 Oct 27 P89C51RC+/P89C51RD+ 28 Product specification ...
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... The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM. — — — — EXTRAM Figure 27. AUXR: Auxiliary Register (RX+ only) 29 Product specification P89C51RC+/P89C51RD+ Reset Value = xxxx xx00B SU00833A ...
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... Applications which use the Watchdog Timer will need to include a series resistor (1 k, 20%) between the reset pin and ANY external components. Without this series resistor the Watchdog Timer will not function OSC OSC 30 Product specification P89C51RC+/P89C51RD+ FFFF EXTERNAL DATA MEMORY 300 (89C51RD+) 0100 0000 SU00885 ...
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... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted. 1999 Oct 27 P89C51RC+/P89C51RD+ RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.0 – ...
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... amb T = – +85 C amb 11 12 ALE and PSEN to momentarily fall below the Freq. CC must be externally limited as follows the voltage specification Product specification P89C51RC+/P89C51RD+ LIMITS UNIT UNIT 1 MIN TYP MAX –0.5 0.2V –0 0.2V +0 ...
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... CLCL 0 6t CLCL 6t CLCL 0 3t CLCL 4t CLCL t CLCL t CLCL 7t CLCL t CLCL 17 17 12t CLCL 10t CLCL 2t CLCL 0 33 Product specification P89C51RC+/P89C51RD+ 4 33MHz CLOCK MAX MIN MAX UNIT 33 MHz 3.5 33 – – – – CLCL – –45 45 ...
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... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPF Figure 30. External Data Memory Read Cycle 34 Product specification P89C51RC+/P89C51RD+ = Time for address valid to ALE low. =Time for ALE low to PSEN low. A0–A7 A8–A15 SU00006 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
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... Figure 32. Shift Register Mode Timing –0.5 0.7V CC 0.2V –0 CHCX CHCL CLCX CLCH t CLCL Figure 33. External Clock Drive 35 Product specification P89C51RC+/P89C51RD+ A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH SU00026 SET TI VALID VALID VALID VALID SET RI SU00027 SU00009 ...
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... level occurs SU00717 Icc ACTIVE MODE (TYP.) Icc IDLE MODE (TYP Frequency at XTAL1 (MHz) Figure 36. I vs. FREQ CC 36 Product specification P89C51RC+/P89C51RD+ V –0.1V TIMING OH REFERENCE POINTS V +0. 20mA SU00718 Figure 35. Float Waveform SU01314 ...
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... CHCL RST P0 EA (NC) XTAL2 XTAL1 V SS SU00016 Test Condition, Power Down Mode 5 Product specification P89C51RC+/P89C51RD RST XTAL2 XTAL1 V SS SU00720 Test Condition, Idle Mode CC All other pins are disconnected SU00009 ...
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... Programmable security for the code in the FLASH. 1000 minimum erase/program cycles for each byte. 10 year minimum data retention. 1999 Oct 27 P89C51RC+/P89C51RD+ CAPABILITIES OF THE PHILIPS 89C51 FLASH-BASED MICROCONTROLLERS FLASH organization (89C51RC+ and 89C51RD+) The 89C51RD+ contains 64 k bytes of FLASH program memory. ...
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... Boot Vector and Status Byte. After programming the FLASH, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H. 39 Product specification P89C51RC+/P89C51RD+ FFFF BOOT ROM FC00 (1k BYTES ON ALL PARTS) 89C51RD+ ...
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... The user thus needs to provide the 89C51RX+ with information required to generate the proper timing. Record type 02 is provided for this purpose. WinISP, a software utility to implement ISP programming with a PC, is available from Philips. 40 Product specification P89C51RC+/P89C51RD+ +12V +5V TxD RxD V SS ...
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... Subfunction Code = 06 (Program Status Byte or Boot Vector program status byte 01 program boot vector Example: :030000030601FCF7 1999 Oct 27 P89C51RC+/P89C51RD+ COMMAND/DATA FUNCTION (dd = 10h = 16, used for 16.0–16.9 MHz 8k, 00H 8k to 16k, 20H erase block 4 erase boot vector and status byte ...
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... Example: :020000050001F8 1999 Oct 27 P89C51RC+/P89C51RD+ COMMAND/DATA FUNCTION display 4000–4FFF read signature byte – device Product specification (C2H) ...
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... Results are returned in the registers. The IAP calls are shown in Table 9. PARAMETER block 8k, 00H block 16k, 20H block 2, 16k to 32k, 40H block 3, 32k to 48k, 80H block 4, 48k to 64k, C0H 01h – security bit # 2 (inhibit Flash verify) 02h – security bit # 3 (disable external memory) 43 Product specification P89C51RC+/P89C51RD+ ...
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... R1 = 07h DPH = 00h DPL = 01h (status byte) Return Parameter ACC = value of byte read READ BOOT VECTOR Input Parameters osc freq (integer 07h DPH = 00h DPL = 02h (boot vector) Return Parameter ACC = value of byte read 1999 Oct 27 P89C51RC+/P89C51RD+ PARAMETER 44 Product specification ...
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... The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The P89C51RC+/P89C51RD+ has three programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 10). ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM DIP40: plastic dual in-line package; 40 leads (600 mil) 1999 Oct 27 P89C51RC+/P89C51RD+ 46 Product specification SOT129-1 ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM PLCC44: plastic leaded chip carrier; 44 leads 1999 Oct 27 P89C51RC+/P89C51RD+ 47 Product specification SOT187-2 ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM QFP44: plastic quad flat package; 44 leads 1999 Oct 27 P89C51RC+/P89C51RD+ 48 Product specification ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 32K/64K ISP FLASH with 512–1K RAM 1999 Oct 27 P89C51RC+/P89C51RD+ NOTES 49 Product specification ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 1999 Oct 27 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 50 Product specification P89C51RC+/P89C51RD+ All rights reserved. Printed in U.S.A. Date of release: 10-99 9397-750-06605 ...