CS5101A-KP8 Cirrus Logic, Inc., CS5101A-KP8 Datasheet
CS5101A-KP8
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CS5101A-KP8 Summary of contents
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... Offset and full-scale errors are minimized dur- ing the calibration cycle, eliminating the need for external trimming. The CS5101A and CS5102A each consist of a 2-chan- nel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architec- ture of the device eliminates the need for an external track and hold amplifier ...
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... CS5101A ; VA+, VD+ = 5V; VA-, VD- = -5V kHz for -16, s CS5101A-A,B Typ Max -40 to +85 - 0.002 0.003 - 0.001 0.002 - - 1 ...
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... This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the HOLD sample rate is 100 kHz max. 8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 s of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 s with an 8 MHz clock, however ...
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... HOLD has fallen. These times are for PDT and RBT modes. clk CS5101A 10%; Min Typ Max Units 108 - 10,000 250 - 10,000 37 37 2.0 - 9.216 MHz 2 ...
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ANALOG CHARACTERISTICS VREF = 4.5V; Full-Scale Input Sinewave, 200 Hz; CLKIN = 1.6 MHz; f AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 AGND unless otherwise specified) Parameter* Specified Temperature Range Accuracy Linearity Error ...
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ANALOG CHARACTERISTICS Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion & Throughput Conversion Time Acquisition Time Throughput Power Supplies Power Supply Current Positive Analog Negative Analog (SLEEP High) Positive Digital Negative ...
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SWITCHING CHARACTERISTICS VA+, VD 10%; VA-, VD- = -5V Parameter CLKIN Period CLKIN Low Time CLKIN High Time Crystal Frequency SLEEP Rising to Oscillator Stable RST Pulse Width RST to STBY Falling RST Rising to STBY Rising CH1/2 ...
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... FRN Mode CH1/2 t dhlri HOLD t hold Channel Selection Timing 8 t rst RST t cal STBY t drrs Reset and Calibration Timing SSH,TRK1,TRK2 t dfsh4 TRK1,TRK2 Control Output Timing CLKIN HOLD CS5101A CS5102A HOLD SSH/SDL t dfsh2 t drsh t dfsh1 b. PDT, RBT Mode Start Conversion Timing t hcf DS45F2 ...
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... CS5102A 6t thfs t chfs ( VA+, VD min max Symbol Min (Note 31 (Note 32) V (VD+)-1 OUT = 1 out CS5101A CS5102A Typ Max Units - - 100 150 ns - 140 230 125 clk clk - clk ...
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... CH1/2 SSH/SDL t rsclk SCLK t sclk t ss SDATA b. SCLK output (SSC and FRN modes) Serial Data Timing TRK1, TRK2 SDATA SCLK b. Register Burst Transmission (RBT) Mode Data Transmission Timing CS5101A CS5102A slkl slkh dss t sh MSB LSB t dts MSB MSB-1 t dss ...
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... Bipolar Notes: 33. All voltages with respect to ground. 34. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binary coding (CODE = low). ...
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... Alternatively, each of the devices can be operated as a single channel ADC operat- ing at 100 kHz (CS5101A kHz (CS5102A). Both the CS5101A and CS5102A can be config- ured to accept either unipolar or bipolar input ranges, and data is output serially in either binary or 2’ ...
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... Calibration The ability of the CS5101A or the CS5102A to convert accurately to 16-bits clearly depends on the accuracy of its comparator and DAC. Each device utilizes an "auto-zeroing" scheme to null errors introduced by the comparator. All offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated ...
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... In fine-charge, the CS5101A can slew unipolar mode. In bipolar mode, only half the capacitor array is connected to the analog input, so the CS5101A can slew at 4V/ s. With a full scale input step, the coarse-charge in- put buffer of the CS5102A will charge the capacitor array within ...
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... LSB above -VREF and the last >(VREF-1.5 LSB) transition occurs 1.5 LSB’s below +VREF. VREF-1.5 LSB The CS5101A and CS5102A can output data in -0.5 LSB either 2’s complement, or binary format. If the CODE pin is high, the output is in 2’s comple- -VREF+0.5 LSB ment format with a range of -32,768 to +32,767 ...
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... PDT RBT SSC FRN Output Mode Control The CS5101A and CS5102A can be configured in three different output modes, as well as an in- ternal, synchronous loop-back mode. This allows great flexibility for design into a wide variety of systems. The operating mode is selected by set- ting the states of the SCKMOD and OUTMOD pins ...
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... Tracking Ch. 1 Converting Ch (Ch. 2) Figure 5. Synchronous Self-Clocking Mode (SSC Tracking Ch. 1 Converting Ch (Ch. 2) Figure 6. Free Run Mode (FRN) CS5101A CS5102A Tracking Ch. 2 Channel 1 Data Tracking Ch. 2 D15 D14 D1 D0 (Ch. 1) ...
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... Later, the CS5101A and CS5102A may be reset at any time to initiate a single full calibration. When RST is brought low all internal logic clears. When RST returns high on the CS5101A, a calibration cycle begins which takes 11,528,160 master clock cycles to complete (approximately 1.4 seconds with an 8 MHz master clock). The ...
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... RST rising. Single-Channel Operation The CS5101A and CS5102A can alternatively be used to sample one channel by tying the CH1/2 input high or low. The unused AIN pin should be tied to the analog input signal or to AGND. (If ...
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... The external reference circuitry need only pro- vide the residual charge required to fully charge the array after coarse-charging from the buffer. This creates an ac current load as the CS5101A and CS5102A sequence through conversions. The reference circuitry must have a low enough out- put impedance to drive the requisite current without changing its output voltage significantly ...
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... The CS5101A and CS5102A can operate with a wide range of reference voltages, but signal-to- noise performance is maximized by using as wide a signal range as possible. The recom- mended reference voltage is 4.5 volts. The CS5101A and CS5102A can actually accept ref- erence voltages up to the positive analog supply ...
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... Fine-charge settling is specified as a maximum of 1.125 s (CS5101A) or 5.625 s (CS5102A) for an analog source impedance of less than 50 addition, the comparator requires a source imped- ance of less than 400 around 2 MHz for stability. The source impedance can be effectively reduced at high frequencies by adding capaci- tance from AIN to ground (typically 200 pF). ...
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... Figures 17 and 19). Figure 11 illustrates the DNL histogram plot of a typical CS5101A Figure 12 illustrates the DNL of the CS5101A at 138 C ambient after calibration ambient. Figures 13 and 14 illustrate the DNL of the CS5102A and 138 C ambient, respectively. A histogram test is a statistical method of deriving an A/D converter’ ...
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... +1 Figure 11. CS5101A DNL Plot; Ambient Temperature 138 C, CAL @ +1 Figure 12. CS5101A DNL Plot; Ambient Temperature at 138 +1 Figure 13. CS5102A DNL Plot; Ambient Temperature 138 C, CAL @ +1 Figure 14. CS5102A DNL Plot; Ambient Temperature at 138 C ...
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... Figure 16. CS5102A DNL Error Distribution tolerance than the DNL plots in Figures 11 and 13 appear to indicate. FFT Tests and Windowing In the factory, the CS5101A and CS5102A are tested using Fast Fourier Transform (FFT) tech- niques to analyze the converters’ dynamic performance. A pure sinewave is applied to the device, and a " ...
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... Un- like conventional successive-approximation ADC’s, the signal-to-noise and dynamic range of the CS5101A and CS5102A are not limited by differential nonlinearities (DNL) caused by cali- bration errors. Rather, the dominant noise source is broadband thermal noise which aliases into the baseband ...
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... All analog circuitry in the CS5101A and CS5102A is wideband in order to achieve fast conversions and high throughput. Wideband noise in the CS5101A and CS5102A integrates rms in unipolar mode (70 V rms in bipo- lar mode). This is approximately 1/2 LSB rms with a 4.5V reference in both modes. Figure 21 ...
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... Its signal-dependency causes distortion at high frequencies. The proprietary architecture of the CS5101A and CS5102A avoids applying the in- put voltage across a sampling switch, thus avoiding any "aperture window" effects. The sec- ond type of aperture jitter, due to component noise, assumes a random nature ...
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... Power Supply Rejection The power supply rejection performance of the CS5101A and CS5102A is enhanced by the on- chip self-calibration and an "auto-zero" process. Drifts in power supply voltages at frequencies less than the calibration rate have negligible ef- fect on the device’ ...
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... Faster Fine Charge Slew Rate (V/ s) Unipolar/Fine Bipolar/Fine Improved Serial Interface CLKIN Rate Code and BP/UP Pin Function CRS/FIN Pin Table 3. CS5101A/CS5102A Improvements over CS5101/CS5102 30 CS5101A/CS5102A No missing codes at +125 C CS5101A CS5102A 2 0.4 4 0.8 Has serial data latch signal (SSH/SDL). CS5101A maximum CLKIN is 9.216 MHz CS5102A maximum CLKIN is 2 ...
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... CS5102A top 9 TRK2 view HOLD CH1/2 SCLK CS5101A CS5102A SLEEP SLEEP (LOW POWER) MODE SCKMOD SERIAL CLOCK MODE SELECT TEST TEST VA+ POSITIVE ANALOG POWER AIN2 CHANNEL 2 ANALOG INPUT VA- NEGATIVE ANALOG POWER AGND ANALOG GROUND REFBUF REFERENCE BUFFER ...
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... Digital Inputs HOLD - Hold, PIN 12. A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run Mode, HOLD is disabled, and should be tied to DGND or VD+. ...
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... Serial data changes status on a falling edge of this input, and is valid on a rising edge. When SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A generates its own serial clock at one-fourth the master clock frequency and SCLK is an output. ...
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... REFBUF - Reference Buffer Output, PIN 21. Reference buffer output. A 0.1 F ceramic capacitor must be tied between this pin and VA-. Miscellaneous TEST - Test, PIN 26. Allows access to the CS5101A’s and the CS5102A’s test functions which are reserved for factory use. Must be tied to VD+. 34 CS5101A CS5102A ...
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... Units in nanoseconds. Aperture Jitter The range of variation in the aperture time. Effectively the "sampling window" which ultimately dic- tates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. DS45F2 CS5101A CS5102A 35 ...
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... CS5101A Ordering Guide Model Conversion Time CS5101A-JP8 8.13 s CS5101A-KP8 8.13 s CS5101A-JP16 16.25 s CS5101A-JL8 8.13 s CS5101A-KL8 8.13 s CS5101A-JL16 16.25 s CS5101A-AP8 8.13 s CS5101A-BP8 8.13 s CS5101A-AL8 8.13 s CS5101A-BL8 8.13 s CS5102A Ordering Guide Model Conversion Time CS5102A- CS5102A- CS5102A- CS5102A- CS5102A- CS5102A- CS5102A- CS5102A- Throughput Linearity Temperature 100 kHz 0 ...
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PIN PLASTIC (PDIP) (600 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.020 A2 0.120 b 0.015 b1 0.030 c 0.008 D 1.380 E 0.600 E1 0.500 0.600 eC 0.000 ...
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PLCC PACKAGE DRAWING DIM MIN A 0.165 A1 0.090 B 0.013 D 0.485 D1 0.450 D2 0.390 E 0.485 E1 0.450 E2 0.390 e 0.040 Apr ’00 : 28L PLCC PACKAGE DRAWING INCHES NOM MAX ...
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PIN LCC PACKAGE DRAWING 1 TOP VIEW D DIM MIN A 0.062 b 0.020 D/E 0.443 D2/E2 0.295 e 0.045 L 0.045 L1 0.075 Apr ’ PIN LCC PACKAGE DRAWING PRELIMINARY PRELIMINARY DRAFT WAITING DRAFT WAITING ON ...
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