LCX14 STMicroelectronics, LCX14 Datasheet

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LCX14

Manufacturer Part Number
LCX14
Description
LCX14LOW VOLTAGE CMOS HEX SCHMITT INVERTER WITH 5V TOLERANT INPUTS
Manufacturer
STMicroelectronics
Datasheet

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© 2005 Fairchild Semiconductor Corporation
74LCX14M
74LCX14MX_NL
(Note 2)
74LCX14SJ
74LCX14BQX
(Note 1)
74LCX14MTC
74LCX14MTCX_NL
(Note 2)
74LCX14
Low Voltage Hex Inverter
with 5V Tolerant Schmitt Trigger Inputs
General Description
The LCX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LCX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
MLP014A
Package
Number
MTC14
MTC14
M14D
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
DS012412
Features
5V tolerant inputs
2.3V–3.6V V
6.5 ns t
Power down high impedance inputs and outputs
r
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
Leadless Pb-Free DQFN package
24 mA output drive (V
Package Description
Machine model
Human model
PD
max (V
CC
specifications provided
CC
!
!
3.3V), 10
CC
2000V
200V
3.0V)
March 1995
Revised February 2005
P
A I
CC
www.fairchildsemi.com
max

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LCX14 Summary of contents

Page 1

... Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs General Description The LCX14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free out- put signals. In addition, they have a greater noise margin than conventional inverters ...

Page 2

Logic Symbol IEEE/IEC Pin Descriptions Pin Names Description I Inputs n O Outputs n Truth Table Input Output www.fairchildsemi.com Connection Diagrams Pin Assignments for SOIC, SOP, and TSSOP Pad Assignments for DQFN L 2 (Top ...

Page 3

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay Time PHL t PLH t Output to Output Skew OSHL t (Note 6) OSLH Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for ...

Page 5

AC Loading and Waveforms ( PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay, Pulse Width and t rec 3-STATE Output High Enable and Disable TImes for Logic (Input Pulse Characteristics 1MHz, ...

Page 6

Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 ...

Page 7

Tape and Reel Specification Tape Format for DQFN Package Tape Designator Section Leader (Start End) BQX Carrier Trailer (Hub End) TAPE DIMENSIONS inches (millimeters) REEL DIMENSIONS inches (millimeters) Tape Size A B 13.0 0.059 12 mm (330) (1.50) Number Cavity ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm www.fairchildsemi.com Package Number MLP014A 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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