SAB-C515A-LM Infineon Technologies AG, SAB-C515A-LM Datasheet
SAB-C515A-LM
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Microcomputer Components 8-Bit CMOS Microcontroller C515A Data Sheet 10.97 ...
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C515A Data Sheet Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Edition 10.97 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All ...
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... CMOS Microcontroller Advance Information • Full upward compatibility with SAB 80C515A/83C515A-5 • MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation • 32K byte on-chip ROM (with optional ROM protection) – alternatively up to 64K byte external program memory • ...
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... Ordering Code SAB-C515A-4RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz) SAF-C515A-4RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz) SAB-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz) SAF-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz) SAB-C515A-LM Q67121-C1068 SAF-C515A-LM Q67121-C1069 SAB-C515A-L24M Q67121-C1070 SAF-C515A-L24M Q67127-C2020 Note: Versions for extended temperature ranges – ...
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XTAL1 XTAL2 ALE PSEN EA RESET PE / SWD HWPD V AREF V AGND Figure 2 Logic Symbol Additional Literature For further information about the C515A the following literature is available: Title C515A 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller ...
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P5.6 61 P5.5 62 P5.4 63 P5.3 64 P5.2 65 P5.1 66 P5.0 67 N.C. 68 HWPD 69 N.C. 70 N.C. 71 P4.0 / ADST 72 P4 SWD 75 P4.3 76 P4.4 ...
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... When left unconnected this pin is pulled high by a weak internal pull-up resistor. Note: If PE/SWD is low and V watchdog is disabled (testmode)! I RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515A. ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) P3.0-P3.7 15- Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit quasi-bidirectional I/O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) P1.0 - P1.7 31 Input O = Output Semiconductor Group ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) XTAL2 36 XTAL1 37 P2.0-P2.7 38-45 PSEN 47 ALE Input O = Output Semiconductor Group I/O*) Function – XTAL2 Input to the inverting oscillator amplifier ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80 P0.0-P0.7 52-59 P5.0-P5.7 67-60 HWPD 69 N.C. 2, 13, 14, 23, 46, 50, 51, 68, 70 Input O = Output Semiconductor Group I/O*) ...
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Oscillator Watchdog XTAl1 OSC & Timing XTAL2 ALE CPU PSEN EA Programmable PE / SWD Watchdog Timer RESET Timer 0 HWPD Timer 1 Timer 2 USART Baud Rate Generator Interrupt Unit V A/D Converter AREF 10-Bit V AGND S&H Figure ...
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CPU The C515A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C515A CPU manipulates operands in the following five address spaces: – Kbyte of program memory (32K on-chip program memory for C515A-4R) – Kbyte of external data memory – 256 bytes of ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator ...
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Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode C 3 MHz C Crystal Mode: Figure 7 Recommended Oscillator Circuitries Semiconductor Group Driving from External Source N.C. XTAL1 External Oscillator Signal ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... SFRs with addresses where address bits 0-2 are 0 (e. … are bitaddressable. The SFRs of the C515A are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C515A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses ...
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... Timer 2, Low Byte T2CON 2) Timer 2 Control Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved Semiconductor Group Address Contents after ...
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... Power Control Register 1 Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... B9 H IP1 XX00- – 0000 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group Bit 6 Bit 5 Bit 4 Bit 3 ...
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... means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit 3 – – – – TF2 IEX6 IEX5 IEX4 COCAL COCA COCAL ...
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... If a digital value read, the voltage levels are to be held within the input voltage specifications ( Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte IL IH instructions. Nevertheless possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4: Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 ...
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C515A provides additional compare/capture/reload features. which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/500 ns resolution – Capture : up to ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the formulas given in table 5. Table ...
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Figure 13 Block Diagram of Baud Rate Generation for the Serial Interface Table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 6 Serial ...
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A/D Converter The C515A provides an A/D converter with the following features: – 8 multiplexed input channels (port 6), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal or ...
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IEN1 ( EXEN2 SWDT IRCON ( EXF2 TF2 ADCON1 ( ADCL ADCON0 ( CLK Port 6 MUX Clock f /2 OSC Prescaler AREF V AGND P4.0 / ADST ...
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Interrupt System The C515A provides 12 interrupt sources with four priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven interrupts may be triggered externally (P3.2/INT0, ...
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... IT0 TCON Converter Timer 0 Overflow P1.4 / NT2 I2FR T2CON.5 P3.3 / INT1 IT1 TCON.2 P1.0 / INT3 CC0 I3FR T2CON.6 Bit addressable Request flag is cleared by hardware Figure 15 Interrupt Request Sources (Part 1) Semiconductor Group IE0 0003 H TCON.1 EX0 IEN0.0 IADC 0043 H IRCON.0 EADC IEN1.0 IP1.0 TF0 ...
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... SCON.0 RI USART TI SCON.1 P1.2 / INT5 / CC2 IRCON.6 Timer 2 TF2 Overflow P1.5/ EXF2 T2EX EXEN2 IRCON.7 IEN1.7 P1.3 / INT6 / CC3 Bit addressable Request flag is cleared by hardware Figure 16 Interrupt Request Sources (Part 2) Semiconductor Group TF1 001B H TCON.7 ET1 IEN0.3 IEX4 005B H IRCON.3 EX4 IEN1.3 IP1.3 <1 0023 H ES IEN0 ...
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Table 7 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External ...
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Fail Save Mechanisms The C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 512 approx. 1 ...
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Oscillator Watchdog The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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EWPD (PCON1.0) P3.2 / INT0 Control Logic Start / Stop RC f Oscillator RC 3 MHz Start / XTAL1 Stop On-Chip XTAL2 Oscillator Figure 18 Block Diagram of the Oscillator Watchdog Semiconductor Group Power-Down Mode Activated Control ...
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Power Saving Modes The C515A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Table 8 Power Saving Modes Overview Mode Entering 2-Instruction Example Idle mode ORL PCON, #01H ORL PCON, #20H Slow Down Mode In normal mode: ORL PCON,#10H With idle mode: ORL PCON,#01H ORL PCON, #30H Software ORL PCON, #02H Power Down ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg Voltage on V pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... CC I – – – – 10 IL2 I – IL3 I – IL4 C – – for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A Unit Test Condition max. 0.2 V – 0.1 V – CC 0.2 V – 0.3 V – 0.1 V – 0.5 V – ...
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... CC XTAL2 driven with CLCH CHCL EA = PE/SWD = Port 0 = Port 6 = all other pins are disconnected (idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL2 driven with CLCH CHCL V RESET = ; HWPD = Port 0 = Port ...
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Figure 19 ICC Diagram Table 9 Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max Idle mode I CC typ I CC max ...
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... ADCC min = 500 ns ADC = OSC CLCL 46 for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A Unit Test Condition Prescaler 8 2) Prescaler 4 ns Prescaler 8 3) Prescaler LSB + 0.5 V ...
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Notes may exceed AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach their ...
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... PXIX t *) – 46 PXIZ – PXAV t – 180 AVIV t 0 – AZPL 48 for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A Limit Values Variable Clock 3.5 MHz to 18 MHz CLCL min. max – 40 – CLCL t – 30 – ...
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AC Characteristics (18 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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... PXIX t *) – 32 PXIZ – PXAV t – 148 AVIV t 0 – AZPL 50 for the SAB-C515A for the SAF-C515A for the SAH-C515A Limit Values Variable Clock 3.5 MHz to 24 MHz CLCL min. max – 40 – CLCL t – 25 – CLCL t – 25 – ...
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AC Characteristics (24 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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ALE PSEN Port 0 Port 2 Figure 20 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 52 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 21 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 22 Data Memory Write Cycle V - 0.5V CC 0.7 V 0.2 0.45V Figure 23 External Clock Drive on XTAL2 ...
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ROM Verification Characteristics for the C515A-1RM ROM Verification Mode 1 Parameter Address to valid data P1.0-P1.7 P2.0-P2.6 Port 0 Data: Addresses: Figure 24 ROM Verification Mode 1 Semiconductor Group Symbol min. t – AVQV Address t AVQV Data Out P0.0-P0.7 ...
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ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 25 ROM Verification Mode 2 Semiconductor Group Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 26 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) Figure 29 P-MQFP-80-1 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 58 C515A ...