SAB-C515-LM Infineon Technologies AG, SAB-C515-LM Datasheet
SAB-C515-LM
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SAB-C515-LM Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C515 Data Sheet 08.97 ...
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C515 Data Sheet Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) Edition 1997-08-01 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All ...
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... CMOS Microcontroller Advance Information Data Sheet • Full upward compatibility with SAB 80C515 • MHz external operating frequency – 500ns instruction cycle at 24 MHz operation • 8K byte on-chip ROM (with optional ROM protection) – alternatively up to 64K byte external program memory • ...
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... Ordering Code SAB-C515-1RM Q67127-DXXXX SAB-C515-1R24M Q67127-DXXXX SAF-C515-1RM Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (16 MHz) SAF-C515-1R24M Q67127-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz) SAB-C515-LM Q67127-C1030 SAB-C515-L24M Q67127-C1032 SAF-C515-LM Q67127-C1031 SAF-C515-L24M Q67127-C1081 Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C515C-LM and SAH- C515-1RM) are available on request ...
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XTAL1 XTAL2 ALE PSEN EA RESET PE V AREF V AGND Figure 2 Logic Symbol Additional Literature For further information about the C515 the following literature is available: Title C515 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller Family Architecture and ...
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P5.6 61 P5.5 62 P5.4 63 P5.3 64 P5.2 65 P5.1 66 P5 N.C. 70 N.C. 71 P4.0 72 P4 P4.3 76 P4.4 77 P4.5 78 ...
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Table 1 Pin Definitions and Functions Symbol Pin Number (P-MQFP-80) RESET 1 VAREF 3 VAGND 4 P6.0-P6.7 12 Input O = Output Semiconductor Group I/O*) Function I RESET A low level on this pin for the duration ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) P3.0-P3.7 15- Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit quasi-bidirectional I/O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) P1.0 - P1.7 31- 33 Input O = Output Semiconductor Group I/O*) ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) XTAL2 36 XTAL1 37 P2.0-P2.7 38-45 PSEN 47 ALE Input O = Output Semiconductor Group I/O*) Function – XTAL2 Input to the inverting oscillator amplifier ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80 P0.0-P0.7 52-59 P5.ß-P5.7 67-60 P4.0-P4.7 72-74, 76- Input O = Output Semiconductor Group I/O*) Function I External Access Enable When held high, ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-80) N.C. 2, 13, 14, 23, 32, 35, 46, 50, 51, 68, 70 Input O = Output Semiconductor Group I/O*) Function – Not connected These pins ...
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C515 XTAL1 OSC & Timing XTAL2 ALE PSEN EA Programmable PE Watchdog Timer RESET Timer 0 Timer 1 Timer 2 USART Baud Rate Generator Interrupt Unit V Programmable AREF V Reference Voltages AGND 8-Bit A/D Converter S & H Figure ...
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CPU The C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C515 CPU manipulates data and operands in the following four address spaces: – Kbyte of internal/external program memory – Kbyte of external data memory – 256 bytes of internal data memory ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator ...
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Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode C 1-24 MHz pF±10 pF (incl. stray capacitance) Crystal Mode : Figure 7 Recommended Oscillator Circuitries Semiconductor Group Driving from ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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... The 59 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0- 2 are 0 (e. ..., are bitaddressable. The SFRs of the C515 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C515 ...
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... Timer 2, Low Byte 2) T2CON Timer 2 Control Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group Address Contents after ...
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... PCON 2) Power Control Register Saving Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group Address Contents after ...
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... IP1 XX00- – 0000 IRCON 00 H EXF2 C1 H CCEN 00 H COCA CCL1 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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... ACC means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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... Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte IL IH instructions. Nevertheless possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 : Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C515 provides additional compare/capture/reload features. which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/500 ns resolution – Capture : up to ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the formulas given in table 5. Table ...
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Timer 1 Overflow ADCON OSC ÷ 39 Mode Mode ÷ 6 Note: The switch configuration shows the reset state. Figure 13 Block Diagram of Baud Rate Generation for the Serial Interface Table 6 below lists the ...
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A/D Converter The C515 provides an A/D converter with the following features: – Eight multiplexed input channels – The possibility of using the analog inputs (port 6) also as digital inputs – Programmable internal reference voltages (16 steps each) ...
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IEN1 (B8 ) EXEN2 SWDT IRCON (C0 ) EXF2 ADCON ( Port ÷ 4 OSC Write to DAPR V AREF V AGND DAPR ( Shaded bit locations are not used in ADC-functions. Figure ...
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Interrupt System The C515 provides 12 interrupt sources with four priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven interrupts may be triggered externally (P3.2/INT0, ...
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... INT0 IT0 TCON.0 A/D Converter Timer 0 Overflow P1.4/ INT2 I2FR T2CON.5 P3.3/ INT1 IT1 TCON.2 P1.0/ INT3 CC0 I3FR T2CON.6 Bit addressable Request Flag is cleared by hardware Figure 15 Interrupt Request Sources (Part 1) Semiconductor Group IE0 0003 EX0 H TCON.1 IEN0.0 IADC 0043 H EADC IRCON.0 IEN1.0 IP1.0 TF0 ...
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... SCON.0 USART TI SCON.1 P1.2/ INT5 CC2 Timer 2 TF2 Overflow IRCON.6 P1.5/ EXF2 T2EX EXEN2 IRCON.7 IEN1.7 P1.3/ INT6 CC3 Bit addressable Request Flag is cleared by hardware Figure 16 Interrupt Request Sources (Part 2) Semiconductor Group TF1 001B ET1 H TCON.7 IEN0.3 IEX4 005B H EX4 IRCON.3 IEN1.3 IP1.3 < ...
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Table 7 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External ...
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... FFFC H and lasts four instruction cycles. This internal reset differs from an external reset only to the extent that the watchdog timer is not disabled. Bit WDTS (was set by starting WDT) allows the software to examine from which source the reset was initiated ...
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Power Saving Modes The C515 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... OH2 0 – – – –10 LI2 I – LI3 I – LI4 C – – for the SAB-C515-1RM for the SAF-C515-1RM for the SAH-C515-1RM Unit Test Condition max. 0 0.1 V – 0.2 - 0.3 V – 0.5 V – 0.5 V – 0.5 V – ...
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... CC XTAL2 driven with CLCH CHCL EA = Port 0 = Port RESET = (idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL2 driven with CLCH CHCL EA = Port 0 = Port RESET = (active mode with slow-down mode) is measured : TBD ...
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Active mode Idle mode Active mode with slow-down f is the oscillator frequency in MHz. OSC Figure 18 ICC Diagram Semiconductor Group CC max CC typ Active Mode with Slow ...
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... The AIN , changes of the analog input voltage have no effect on the conversion S and the conversion time 4 guaranteed by design characterization for all AGND CC 44 for the SAB-C515-1RM for the SAF-C515-1RM for the SAH-C515-1RM IntAREF IntAGND Unit ...
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... LLSH t 85 – SHSL t 585 – SLSH t 23 103 SLLH 45 for the SAB-C515-1RM for the SAF-C515-1RM for the SAH-C515-1RM Limit Values Variable Clock MHz to 16 MHz CLCL min. max – 40 – CLCL t – 30 – CLCL t – ...
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AC Characteristics (16 MHz) (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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... Clock min. max. t 252 – LLSH t 43 – SHSL t 377 – SLSH SLLH 47 for the SAB-C515-1RM for the SAF-C515-1RM for the SAH-C515-1RM Limit Values Variable Clock MHz to 24 MHz CLCL min. max – 40 – CLCL t – 25 – CLCL t – ...
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AC Characteristics (24 MHz) (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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ALE PSEN Port 0 Port 2 Figure 19 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t t AZPL PXAV t t LLAX PXIZ t PXIX Instr.IN ...
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ALE PSEN RD t AVLL from Port DPL Port 2 Figure 20 Data Memory Read Cycle Figure 21 CLKOUT Timing Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ ...
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ALE PSEN WR t AVLL from Port DPL Port 2 Figure 22 Data Memory Write Cycle V - 0.5V CC 0.45V Figure 23 External Clock Drive at XTAL2 Semiconductor Group t t LLWL WLWH ...
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ROM Verification Characteristics for the C515-1RM ROM Verification Mode 1 Parameter Address to valid data P1.0 - P1.7 P2.0 - P2.4 Port 0 Address : P1 P2 A12 Data ...
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ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 25 ROM Verification Mode 2 Semiconductor Group Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 26 AC Testing: Input, Output Waveforms V +0.1 V Load V Load V Load For timing purposes a port pin is ...
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Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) Figure 29 P-MQFP-80-1 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 55 C515 ...