STV8217 STMicroelectronics, STV8217 Datasheet

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Key Features ■ Full-Automatic Multi-Standard Demodulation Standards ● ● Mono AM and FM FM 2-Carrier (German and Korean Zweiton) and ● NICAM ■ Multi-Channel ...

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Block Diagram 2/149 Digital Audio Matrix Pre-scaler STV82x7 XTALOUT XTALIN CLK_SEL ...

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STV82x7 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Beeper ................................................................................................................................ 37 Chapter 5 Analog Audio Matrix (In / Out ...

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STV82x7 12.12 Automatic Standard Recognition ........................................................................................ 81 12.13 Audio Preprocessing and Selection Registers ................................................................... 85 12.14 Matrixing ............................................................................................................................. 93 12.15 Audio Processing ............................................................................................................... 98 12.16 5-Band Equalizer / Bass-Treble for Loudspeakers .......................................................... 112 12.17 Headphone Bass-Treble .................................................................................................. 113 12.18 Volume ...

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General Description 1 General Description The STV82x7 is a multistandard TV sound demodulator and audio processor which integrates SRS® WOW™, SRS® TruSurround XT™, Dolby® Pro Logic®, Dolby® Pro Logic II®,Virtual Dolby® Surround (VDS) and Virtual Dolby® Digital (VDD) capability. ST ...

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STV82x7 Demodulation X AM/FM - Mono, FM 2-carrier NICAM Multi-Channel Capability 3 x I² I²S Out, S/PDIF (Pass-thru) 5.1 Analog Out for Loudspeakers Virtual Dolby® Surround 1 Virtual Dolby® Digital ...

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General Description 1.1 STV82x7 Overview 1.1.1 Core Features Single audio source processing: ● — IF source and/or analog stereo input (SCART) — one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S) SIF input ...

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STV82x7 Specific stand-by mode (Loop-through) ● Control by I²C bus (two I²C addresses) ● System PLL and Clock Generation using either a single quartz oscillator or a differential clock ● input 1.1.2 Software Information The different software combinations are listed ...

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General Description — External audio input interface using 3 x I²S (for decoded streams such as Dolby® Digital and/or standard stereo streams) 1.1.4 Electrical Features Multi Power Supply: 1.8 V, 3.3 V and 8 V. Power Consumption: lower than 1 ...

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STV82x7 Figure 2: STV8237 Typical Application (Enhanced Stereo) Tuner or Left Right Figure 3: STV8247 Typical Application (Analog Virtual Sound) Tuner or Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XT STV8237 Multistandard Demodulation - FM ...

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General Description Figure 4: STV8257 Typical Application (Digital: Virtual Sound) Multi-Channel Digital Decoder ® (Dolby Digital) I²S Tuner or Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XT 2. When using VDD with ST OmniSurround or ...

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... STV82x7 Figure 6: STV8217 Typical Application (Digital Recorder) Tuner or MPEG Codec I²S STV8217 Multistandard Demodulation - FM 2-carrier and NICAM Left Right General Description 13/149 ...

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General Description 1.3 Pin Descriptions and Application Diagrams AP = Analog Power ● Digital Power ● Input ● Output ● Open-Drain ● Bi-Directional ● Analog ● Pin STV82x7 ...

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STV82x7 Pin STV82x7 Type No. Pin Name (STV82x7) 23 SC3_IN_L 24 SC3_IN_R 25 SCL_FLT 26 SCR_FLT 27 LS_C 28 LS_L 29 LS_R 30 LS_SUB 31 HP_LSS_L 32 HP_LSS_R 33 VSS18_CONV DP 34 VDD18_CONV DP 35 HP_DET 36 ADR_SEL 37 VSS18 ...

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General Description Pin STV82x7 Type No. Pin Name (STV82x7) 53 XTALOUT_CLKXTM 54 VCC18_CLK1 AP 55 GND18_CLK1 AP 56 GND18_CLK2 AP 57 VCC18_CLK2 DP 58 VSS33_IO2 DP 59 VDD33_IO2 DP 60 I2S_PCM_CLK I/O 61 I2S_SCLK I/O 62 I2S_LR_CLK I/O 63 I2S_DATA0 ...

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STV82x7 Figure 7: STV82x7 Application Diagram + + + + + + + + + + + VSS33_CONV 21 VDD33_CONV 22 SC3_IN_L 23 SC3_IN_R 24 SCL_FLT 25 SCR_FLT 26 LS_C 27 LS_L 28 LS_R 29 LS_SUB 30 HP_LSS_L 31 HL_LSS_R ...

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General Description Figure 8: STV82x6/STV82x7 Compatible Application Electrical Diagram 18/149 + + + + + + + + + + + VSS33_CONV 21 VDD33_CONV 22 SC3_IN_L 23 SC3_IN_R 24 SCL_FLT 25 SCR_FLT 26 LS_C 27 LS_L 28 LS_R 29 LS_SUB ...

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STV82x7 Figure 9: STV82x7/STV82x8 Compatible Application Electrical Diagram (TQFP80 VSS33_CONV 21 VDD33_CONV 22 SC3_IN_L ...

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System Clock 2 System Clock The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer can be used in one of two modes: In Mode used by the demodulator, and the frequecy is 49.152 MHz. ...

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STV82x7 3 Digital Demodulator The Digital Demodulator (see demodulates signal. The second channel demodulates FM 2-carrier or NICAM signals (stereo demodulation). All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) ...

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Digital Demodulator 3.2 Demodulation The demodulation system operates by default in Automatic mode. In this mode, the STV82x7 is able to identify and demodulate any TV sound standard including NICAM and A2 systems (see Table 4) without any external control ...

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STV82x7 System Sound Type Name D/K2 FM 2-Carrier D/K3 FM 2-Carrier FM Mono I FM/NICAM L AM/NICAM FM Mono M/N FM 2-Carrier For Chinese TV transmissions (DK-NICAM) which are subject to overmodulation, different FM deviations are proposed for sound demodulation. ...

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Dedicated Digital Signal Processor (DSP) 4 Dedicated Digital Signal Processor (DSP) A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure ...

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STV82x7 The main features depend on the path: FM Channel ● — DC Removal — Prescaling — De-emphasis ( us) — Stereo Dematrix NICAM Channel ● — DC Removal — Prescaling — De-emphasis (J17) — Dematrix Input SCART ...

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Dedicated Digital Signal Processor (DSP) Balance ● Beeper ● Pink Noise Generator (used to position the loudspeakers) ● Programmable Delay for each loudspeaker ● Adjustable Delay for “lip sync” 120 ms (to compensate audio/video latency) in SCART ● ...

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STV82x7 Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs Dedicated Digital Signal Processor (DSP) Select output 27/149 ...

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Dedicated Digital Signal Processor (DSP) 4.3 ST WideSurround STV82x7 offers three preset ST WideSurround Sound effects on the Loudspeakers path: Music, a concert hall effect ● Movie, for films on TV ● Simulated Stereo, which generates a pseudo-stereo effect from ...

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STV82x7 Speakers that have limited bass handling capabilities will be referred to as “satellite speakers”, then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82x7, five output configuration modes have ...

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Dedicated Digital Signal Processor (DSP) 4.6.2 Bass Management Configuration 1 Configuration 1, shown in the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal ...

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STV82x7 4.6.3 Bass Management Configuration 2 Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This ...

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Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3 The third configuration, shown in range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to ...

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STV82x7 4.6.5 Bass Management Configuration 4 This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left ...

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Dedicated Digital Signal Processor (DSP) is processed by an identical HRTF curve but mixed much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The ...

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STV82x7 The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode ( SubW). 4.9 ST Dynamic Bass STV82x7 offers dynamic bass boost ...

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Dedicated Digital Signal Processor (DSP) 4.12 Automatic Loudness Control As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the ...

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STV82x7 In Independent mode, the volume for the Left and Right channels for Loudspeakers or ● Headphone is controlled independently. 100% Mute 4.14 Soft Mute Control The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to ...

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Dedicated Digital Signal Processor (DSP) A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be ...

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STV82x7 5 Analog Audio Matrix (In / Out) The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix. S1in S2in S3in S4in MONO_in The SCART input matrix is ...

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I²S Interface (In / Out) 6 I²S Interface (In / Out) The STV82x7 offers three input/output choices: one I²S input, three I²S inputs or one I²S output. 6.1 I²S Inputs The STV82x7 can interface with a digital sound decoder. In ...

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STV82x7 I²S (Max. Number of Channels) 1 (I²S_DATA0) 1 (I²S_DATA0 (I²S_DATA0) 1 (I²S_DATA0 (I²S_DATA0) 1 (I²S_DATA0) 3 Both standard and non-standard modes are available, see 6.2 I²S Output A digital stereo output (I²S compatible) is also ...

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S/PDIF Input/Output 7 S/PDIF Input/Output An S/PDIF output is available for connection with an external decoder/amplifier. An internal multiplexer allows selection of either the internal signal or the external signal connected on the SPDIF input (for example, the signal provided ...

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STV82x7 8 Power Supply Management A mixed supply voltage environment requires the following voltages: 3.3V capable inputs/outputs for digital pins; ● 1.8V digital core; ● 8V capable inputs/outputs for analog audio interfaces (capability to output 2 V ● requirements); 3.3V ...

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Additional Controls and Flag 9 Additional Controls and Flag This logic contains: the headphone detection, ● the IRQ generation, signal to be output to the MCU, ● the I²C bus expander output pin. ● 9.1 Headphone Detection For headphone, the ...

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STV82x7 10 STV82x7 Reset All STV82x7 features are controlled via the I²C bus. The STV82x7 can be "reset" ways Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers. 2. ...

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I²C Interface 11 I²C Interface 11.1 I²C Address and Protocol The STV82x7 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are ...

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STV82x7 11.2 Start-up and Configuration Change Procedure Figure 27: Flow chart Power ON NOTE: This HW reset after Power ON is Hardware Reset (by pin 43) mandatory to avoid bad device configuration Clock PLLs progammation (FS1 & FS2 registers) (for ...

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Register List 12 Register List Note: The unused bits (defined as ‘Reserved’) in the I²C registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to ...

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STV82x7 12.1 I²C Register Map By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Name Addr. IC General Control CUT_ID 00h (0000 ...

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Register List Name Addr. CAROFFSET1 22h 0000 0000 Demodulator Channel 2 IAGCR 25h 1000 1000 IAGCC 26h 0000 0011 IAGCS 27h (0000 0000) CARFQ2H 28h 0100 0100 CARFQ2M 29h 0100 0000 CARFQ2L 2Ah 0000 0000 FIR2C0 2Bh 0000 0000 FIR2C1 ...

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STV82x7 Name Addr. FS2_DIV 5Ah 0001 0001 FS2_MD 5Bh 0001 0001 FS2_PE_H 5Ch 0101 1100 FS2_PE_L 5Dh 0010 1001 DSP Control HOST_CMD 80h 0000 0000 IRQ_STATUS 81h 0000 0000 SOFT_VERSION 82h (0000 0002) ONCHIP_ALGOS 83h (0000 0000) DSP_STATUS 84h 0000 ...

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Register List Name Addr. PEAK_DET_INPUT 9Dh 0000 0000 PEAK_DET_L 9Eh PEAK_DET_R 9Fh PEAK_DET_L_R A0h Matrixing AUDIO_MATRIX_INPUT A2h 0000 0000 AUDIO_MATRIX_CONFIG A3h 0000 0000 AUDIO_MATRIX_LANGUAGE A4h 0000 0000 DOWNMIX_IN_MODE A6h 0000 0010 DOWNMIX_OUT_MODE A7h 0100 1010 DOWNMIX_DUAL_MODE A8h 0000 0000 DOWNMIX_CONFIG ...

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STV82x7 Name Addr. SVC_HP_TIME_TH C1h 1001 1000 SVC_LS_GAIN C2h 0000 0000 SVC_HP_GAIN C3h 0000 0000 STSRND_CONTROL C4h 0000 0000 STSRND_FREQ C5h 0001 0101 STSRND_LEVEL C6h 1000 0000 OMNISURROUND_CONTROL C7h 0000 0000 ST_DYNAMIC_BASS C8h 0000 0000 LS_EQ_BT_CTRL C9h 0000 0000 LS_EQ_BAND1 ...

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Register List Name Addr. LS_SR_VOLUME_LSB E3h 0000 0000 LS_MASTER_VOLUME_MSB E4h 1110 1000 LS_MASTER_VOLUME_LSB E5h 0000 0000 HP_L_VOLUME_MSB E6h 1001 1000 HP_L_VOLUME_LSB E7h 0000 0000 HP_R_VOLUME_MSB E8h 0000 0000 HP_R_VOLUME_LSB E9h 0000 0000 SCART_L_VOLUME_MSB EAh 1101 1101 SCART_L_VOLUME_LSB EBh 0000 0000 ...

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STV82x7 12.2 STV82x7 General Control Registers CUT_ID Address: 00h Type: R Bit 7 Bit Bit Name Reset Bits[7:6] 00 Reserved CUT_NUMBER[5:0] 000001 Dice Version Identification RESET Address: 01h Type: R/W Bit 7 Bit 6 BUS_EXP I²S_OUTPUT Description ...

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Register List I2S_CTRL Address: 04h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 0 Reserved. LR_OFF 0 LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected LOCK_FLAG 0 Lock Flag allowing ...

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STV82x7 necessary, the PLL Clock can be re-programmed for other quartz crystal frequencies within a range from MHz. Other quartz crystal frequencies can be programmed on your demand. Note: A Crystal Frequency change is compatible with other ...

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Register List Bit Name Reset Bit 6 0 Reserved. NDIV1[1:0] 01 FS1 Input clock divider selection Bit 3 0 Reserved. SDIV1[2:0] 010 FS1 Output clock divider selection FS1_MD Address: 09h Type: R/W Bit 7 Bit Bit Name ...

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STV82x7 Bit Name Reset PE_L1[7:0] 0000 FS1 Fine Selection (LSBs) 0000 12.4 Demodulator DEMOD_CTRL Address: 0Ch Type: R/W Bit 7 Bit FAR_MODE Bit Name Reset bit [7:6] 000 Reserved FAR_MODE 0 1: Farrow and Mono filter for ...

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Register List Bit Name Reset Bit [7:5] 000 Reserved. QPSK_LK 0 QPSK Lock Detection Flag 0: Not detected 1: Detected FM2_CAR 0 Channel 2 FM/AM Carrier Detection Flag 0: Not detected 1: Detected FM2_SQ 0 Channel 2 FM Squelch Detection ...

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STV82x7 Bit Name Reset AGC_CST[1:0] 01 AGC Time Constant This is the time constant between each step of 1 the AGC AGC_GAIN Address: 0Fh Type: R/W Bit 7 Bit 6 0 Bit Name Reset ...

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Register List DC_ERR_IF Address: 10h Type: R Bit 7 Bit 6 Bit Name Reset DC_ERR[7:0] 00000000 DC offset error of IF ADC output 12.5 Demodulator Channel 1 CARFQ1H, CARFQ1M, CARFQ1L Address: 12h to 14h Type: R/W Bit 7 Bit 6 ...

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STV82x7 FIR1C[0:7] Address: 15h to 1Ch Type: R/W Bit 7 Bit 6 Bitfield FM 27 kHz FIR1C0[7:0] FFh FIR1C1[7:0] FEh FIR1C2[7:0] FEh FIR1C3[7:0] 00h FIR1C4[7:0] 06h FIR1C5[7:0] 0Eh FIR1C6[7:0] 16h FIR1C7[7:0] 1Bh ACOEFF1 Address: 1Dh Type: R/W Bit 7 Bit ...

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Register List BCOEFF1 Address: 1Eh Type: R/W Bit 7 Bit 6 Bit Name Reset Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain BCOEFF1[7:0] 00010010 Defines the bandwidth of the loop. For values, refer ...

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STV82x7 Bit Name Reset CETH1[7:0] 00100000 This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 ...

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Register List 12.6 Demodulator Channel 2 IAGCR Address: 25h Type: R/W Bit 7 Bit 6 Bit Name Reset IAGC_REF[7:0] 10001000 Sets the mean value of the internal AGC, used for QPSK demodulation. The default setting corresponds to half full scale ...

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STV82x7 IAGCS Address: 27h Type: R Bit 7 Bit 6 Bit Name Reset IAGC_CTRL[7:0] 00000000 Indicates the value of the internal AGC gain control CARFQ2H, CARFQ2M, CARFQ2L Address: 28H to 2Ah Type: R/W Bit 7 Bit 6 Bit Name Reset ...

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Register List FIR2C[0:7] Address: 2Bh to 32h Type: R/W Bit 7 Bit 6 Bitfield FIR2C0[7:0] FIR2C1[7:0] FIR2C2[7:0] FIR2C3[7:0] FIR2C4[7:0] FIR2C5[7:0] FIR2C6[7:0] FIR2C7[7:0] ACOEFF2 Address: 33h Type: R/W Bit 7 Bit 6 Bit Name Reset ACOEFF2[7:0] 10010000 This value defines the ...

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STV82x7 Bit Name Reset BCOEFF2[7:0] 10101100 This value defines the loop bandwidth used to program the Integral Coefficient of the Baseband PLL loop filter and DCO gain. See Table 15: Baseband PLL Loop Filter Adjustments (FM Mode) FM mode ACOEFF ...

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Register List SRF Address: 36h Type: R/W Bit 7 Bit 6 Bit Name Reset SRF[7:0] 00000000 Displays in two’s complement format the frequency deviation between the incoming NICAM bitstream and the quartz clocks. The maximum error is ±250 ppm. CRF2 ...

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STV82x7 SQTH2 Address: 39h Type: R/W Bit 7 Bit 6 Bit Name Reset SQTH2[7:0] 00111100 The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is ...

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Register List Bit Name Reset Bits[7:3] 00000 Reserved. DIF_POL polarity inversion (Default) 1: Polarity inversion of the differential decoding ECT 0 Error Counter Timer: Defines the NICAM error measurement period 0: 128 ms (Default ...

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STV82x7 12.8 Stereo Mode ZWT_CTRL Address: 40h Type: R/W Bit 7 Bit 6 LRST_TONE_OFF STD_MODE Bit Name Reset LRST_TONE_OFF 0 Control of the reset of the tone detector 0: Periodical reset of tone detection enabled 1: Periodical reset of tone ...

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Register List Bit Name Reset ZWT_TIME[2:0] 100 Defines the period of the reset tone used for tone detection system reset. 000 001 010 011 100 101 110 111 ZWT_STAT Address: 42h Type: R Bit 7 Bit 6 LRST_TONE_ 0 OFF ...

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STV82x7 Bit Name Reset I2S_DATA0_CTRL[1: SCART Srnd 11 = C/Sub Bits[7:4] 0000 Reserved. ADC_POWER_UP 1 Control of the power up of the Audio ADC 0: ADC in power down ...

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Register List SCART3_OUTPUT_CTRL Address: 58h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:4] 0000 Reserved. 1 Mute command for the output SCART 3 SC3_MUTE 0: output not muted 1: output muted SC3_OUTPUT_SEL[2:0] 011 Selection of the ...

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STV82x7 Bit Name Reset Bits[7:5] 000 Reserved. MD2[4:0] 10001 FS2 Coarse Selection FS2_PE_H Address: 5Ch Type: R/W Bit 7 Bit 6 Bit Name Reset PE_H2[7:0] 0101 FS2 Fine Selection (MSBs) 1100 FS2_PE_L Address: 5Dh Type: R/W Bit 7 Bit 6 ...

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Register List Bit Name Reset HW_RESET 0 DSP Hardware reset when set. Bits[1:0] 00 Reserved. IRQ_STATUS Address: 81h Type: R/W Bit 7 Bit 6 IRQ7 IRQ6 Bit Name Reset Bits[7:4] 0000 Reserved. IRQ3 0 Unmute HP/Srnd DAC IRQ IRQ2 0 ...

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STV82x7 Bit Name Reset Bit 7 0 Reserved. PRO_LOGIC_SELECT 0: Dolby Pro Logic Dolby Pro Logic II NICAM 0 NICAM Demodulator is present when set. I2S_INPUT 0: 1 I2S input I2S inputs DIALOG_CLARITY 0 ...

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Register List Bit Name Reset TEST_MODE[5: standard configuration 1: bypass processing configuration 2: Clock Loop test Bits[3:2] 00 Reserved HOST_ NO_INIT 0 0: I2C register table is initialized when we soft reset 1: I2C register table is not ...

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STV82x7 Bit Name Reset DELAY_TIME Audio Delay Time 0000000 ... 0000000 0111100 (48kHz) ... 1011010 (32kHz) DELAY_ON 0 Audio/video delay is enabled when set. Note: AV_DELAY acts on both LS and HP paths simultaneously ...

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Register List L/L’ and DK/K1/K2/K3 standard cannot be discriminated in Automatic Standard Recognition Search mode because the same frequency is used for the mono IF carrier. AUTOSTD_STANDARD_DETECTAuto Standard Check Standard Register Address: 8Bh Type: R/W Bit 7 Bit 6 NICAM_C4_O ...

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STV82x7 Bit Name Reset LDK_ZWT3 D/K3 Zweiton (A2*) Stereo Standard Enable 0 0: Disabled 1: Enabled LDK_ZWT2 D/K2 Zweiton (A2*) Stereo Standard Enable 0 0: Disabled 1: Enabled LDK_ZWT1 D/K1 Zweiton (A2*) Stereo Standard Enable 0 0: Disabled 1: Enabled ...

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Register List Bit Name Reset ZWEITON_TIME[2:0] Zweiton Detection Time-out 000: forbidens 100 001: 512 ms 010: 768 ms 011: 1024 ms Note: The time-out default value is optimum and does not normally need to be changed. AUTOSTD_STATUS Address: 8Eh Type: ...

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STV82x7 Mono Sound MONO_SID System (MHz) L 6.5 (AM) 6.5 (FM 50k) 6.5 (FM 200k) D/K 6.5 (FM 350k) 6.5 (FM 500k) D/K1/K2/ 6.5 (FM 50k) K3 Note: X means don’t care. 12.13 Audio Preprocessing and Selection Registers DC_REMOVAL_INPUT Address: ...

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Register List DC_REMOVAL_L Address: 91h Type: R Bit 7 Bit 6 Bit Name Reset DC_REMOVAL_L[7:0] Displays (in two’s complement format) the FM (or AM) DC offset level after demodulation on channel 1 (and removed automatically mode, the DC ...

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STV82x7 PRESCALE_SELECT Address: 93h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:1] 0000000 Reserved. AM_FM_SELECT prescale is applied to demodulator channels 1: AM prescale is applied to demodulator channels PRESCALE_AM Address: 94h Type: ...

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Register List Bit Name Reset Bit 7 0 Reserved. PRESCALE_FM[6:0] 0001100 - prescaling to normalize the FM demodulated signal level before audio processing. Auto level control can be implemented by I2C software using the Peak ...

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STV82x7 Bit Name Reset PRESCALE_ 0000000 - SCART prescaling to normalize the SCART signal level before audio SCART[5:0] processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = ...

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Register List Bit Name Reset PRESCALE_I2S_1[5:0] 000000 - I2S_1 prescaling to normalize the I2S_1 signal level before audio processing. Auto level control can be implemented by I2C software using the Peak Level Detector. (Default value = ...

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STV82x7 Bit Name Reset NICAM_DEMATRIX 0 Dematrixing for NICAM demodulator input: 00: L=ch0, R=ch1 01: L=ch1, R=ch0 NICAM_DEEMPH_ 0 0: NICAM deemphasis is not bypassed. BYPASS 1: NICAM deepmhasis is bypassed. FM_DEMATRIX[3:2] 00 Dematrixing for FM demodulator input: 00: L=ch0, ...

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Register List Bit Name Reset OVERLOAD_L[7] 0 Memorise overload on the peak detection. This field can be reset. PEAK_L[6:0] 00000000 Displays the Absolute Peak Level of the audio source selected. The measured value is updated continuously every 64 ms. The ...

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STV82x7 12.14 Matrixing AUDIO_MATRIX_INPUT Address: A2h Type: R/W Bit 7 Bit Bit Name Reset Bits [7:3] 00000 Reserved. SCART_INPUT_ 0 Select input source for SCART output: SOURCE 0: Demod 1: SCART input HP_INPUT_ 0 Select input source ...

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Register List Input Mode Language -> demod_mx Mono AM/FM 0000 with backup Mono AM/FM 0001 no backup Zwt St 0100 Zwt Dual 0101 NICAM Mn, backup 1000 NICAM Dual backup 1001 NICAM St, backup 1010 NICAM Mn, no backup 1100 ...

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STV82x7 Bit Name Reset MUTE_STEREO 0 Mute outputs with stereo signal input MUTE_ALL 0 Mute all outputs SCART_ 00 Select language for SCART output LANGUAGE[1:0] HP_LANGUAGE[1:0] 00 Select language for HPoutput 00 Select language for LS output 00: stereo LS_LANGUAGE[1:0] ...

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Register List DOWNMIX_OUT_MODE Address:A7h Type: R/W Bit 7 Bit 6 0 HP_MODE[1:0] Bit Name Reset Bit 7 0 Reserved. HP_MODE[1:0] 10 see SCART_MODE[1:0] 01 see LS_OUT_MODE [2:0] 010 see Parameter Coding (Decimal Format Parameter Coding (Decimal ...

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STV82x7 DOWNMIX_DUAL_MODE Address: A8h Type: R/W Bit 7 Bit 6 0 DUAL_ON LS_DUAL_SELECT[1:0] Bit Name Reset Bit 7 0 DUAL_ON 0 LS_DUAL_SELECT[1:0] 00 SCART_DUAL_SELECT[1:0] 00 HP_DUAL_SELECT[1:0] 00 DOWNMIX_CONFIG Address: A9h Type: R/W Bit 7 Bit Bit Name ...

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Register List Bit Name Reset LR_UPMIX 0 0: disable upmixing 1: enable upmixing (DTS specified) NORMALIZE 1 0: disable normalization 1: enable normalization 12.15 Audio Processing PRO_LOGIC2_CONTROL Address: AAh Type: R/W Bit 7 Bit 6 PL2_LFE PL2_OUTPUT_DOWNMIX[2:0] Bit Name Reset ...

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STV82x7 Table 26: Prologic II Decode Mode Configuration (Continued) PL2 Decode Mode Dimension Mode Movie/ 3 Standard 4 Matrix 5 Custom Note user defined parameter) PCM_SRND_DELAY Address: ABh Type: R/W Bit 7 Bit Bit Name ...

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Register List PRO_LOGIC2_CONFIG Address: ADh Type: R/W Bit 7 Bit 6 Bit 5 PL2_LFE 0 Bit Name Reset Bits[7:6] 00 Reserved. 00: 0: Off 01: 1: Shelf Filter (for music and matrix modes) PL2_SRND_FILTR[1:0] 00 10: 2: 7kHz LP 11: ...

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STV82x7 Bit Name Reset 000: -3, most surround 001: -2 010: -1 011: 0, neutral = OFF PL2_DIMENSION[2:0] 000 100: 1 101: 2 110:3, most center 111: not applicable See Table 26: Prologic II Decode Mode Configuration the decode mode. ...

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Register List Bit Name Reset LEFT_NOISE 0 1: Generates noise on LS left output 0: Noise Generation not active NOISE_ON 0 1: Noise Generation is active TRUSRND_CONTROL Address: B1h Type: R/W Bit 7 Bit 6 TRUSRND_ 0 MONO_SRND Bit Name ...

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STV82x7 Bit Name Reset TRUSRND_INPUT_ 0000 Input Gain attenuation: GAIN[7:0] 0000 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB TRUSRND_HP_DCL Address: B7h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 00000 Reserved. DIALOG_ 0 ...

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Register List TRUBASS_LS_CONTROL Address: BAh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:3] 00000 Reserved. TRUBASS_LS_SIZE[2:0] 000: LF response at 40Hz 001: LF response at 60Hz 010: LF response at 100Hz 011: LF response at 150Hz ...

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STV82x7 Bit Name Reset Bits[7:3] 00000 Reserved. TRUBASS_HP_ 000: LF response at 40Hz SIZE[2:0] 001: LF response at 60Hz 010: LF response at 100Hz 011: LF response at 150Hz 011 100: LF response at 200Hz 101: LF response at 250Hz ...

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Register List SVC_LS_TIME_TH Address: BFh Type: R/W Bit 7 Bit 6 SVC_LS_TIME[2:0] Bit Name Reset SVC_LS_TIME[2:0] Time constant for the amplification (6dB gain step) in automatic mode: 000: 30ms 001: 200ms 010: 500ms 100 011: 1s 100: 16s 101: 32s ...

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STV82x7 SVC_HP_CONTROL Address: C0h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. SVC_LHP_AMP 0: 0dB amplification in auto-mode 1 1: +6dB amplification in auto-mode SVC_HP_ON 0 0: Manual mode (simple prescaler) 1: Automatic mode ...

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Register List Bit Name Reset SVC_HP_TIME[2:0] 100 Time constant for the amplification (6dB gain step) in automatic mode: 000: 30ms 001: 200ms 010: 500ms 011: 1s 100: 16s 101: 32s 110: 64s 111: 128s SVC_HP_ 11000 see Table 27 THRESHOLD[4:0] ...

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STV82x7 Bit Name Reset SVC_HP_GAIN[6:0] Set “make-up” gain applied at SVC HP output: 0000000: 0000001: 0000000 ... 0101110: 0101111: 0110000: STSRND_CONTROL Address: C4h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:3] 00000 Reserved. STSRND_STEREO 0 ST ...

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Register List Bit Name Reset STSRND_TREBLE[1:0] 01 Defines the treble frequency effect for ST WideSurround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in BASS_FREQ[1: (Default STSRND_LEVEL Address: C6h ...

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STV82x7 Bit Name Reset 00: OFF 01: Low ST_VOICE[1:0] 00 10: Mid 11: High FRONT_BYPASS 0 Forced to 0 OMNISRND_ 000: Mono INPUT_ MODE[3:0] 001: L/R stereo 010: L/R/S 011: L/R/Ls/Rs 0000 100: L/R/C 101: L/R/C/S 110: L/R/C/Ls/Rs 111: Lt/Rt ...

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Register List 12.16 5-Band Equalizer / Bass-Treble for Loudspeakers LS_EQ_BT_CTRL Address: C9h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. LS_EQ_BT_SW 0 5-Band Equalizer or Bass-Teble selection 0: 5-Band Equalizer is selected for Loudspeakers. ...

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STV82x7 Table 30: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values) LS_BASS_GAIN Address: CFh Type: R/W Bit 7 Bit 6 Bit Name Reset LS_BASS[7:0] 0000 Bass gain adjustment within a range from - + steps ...

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Register List Bit Name Reset HP_EQ_ON 1 Bass-Treble for headphone Enable 0: Bass-Teble is disabled 1: Bass-Teble is enabled (Default) HP_BASS_GAIN Address: D2h Type: R/W Bit 7 Bit 6 Bit Name Reset HP_BASS_ 00000000 Gain Tuning of Headphone Bass Frequency ...

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STV82x7 Bit Name Reset BASS_MANAGE_ON 1 0: BassManagement disables 1: BassManagement enabled Bit 6 0 Reserved. SUB_ACTIVE 0 0: Subwoofer output is disabled (only in config 2,3,4) 1: Subwoofer output is active GAIN_ 0 0: Level adjustment ON SWITCH 1: ...

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Register List HP_LOUDNESS Address: D6h Type: R/W Bit 7 Bit 6 0 HP_LOUD_THRESHOLD[2:0] Bit Name Reset Bit 7 0 Reserved. HP_LOUD_ 000 Define the volume threshold level since which loudness effect is applied : THRESHOLD[2:0] 000: 0dB 001: -6dB 010: ...

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STV82x7 Bit Name Reset ANTICLIP_LS_VOL 1 The output level is clamped depending on the LS Equalizer or LS Bass-Treble value to avoid any _CLAMP possible signal clipping on LS output. 0: Volume clamp on LS output is not active 1: ...

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Register List Bit Name Reset LS_L_VOLUME_ bits volume Left channel 2 LSB in independent mode bits volume Left and Right LSB[1:0] channels 2 LSB in differential mode. See Figure 19: Volume Control on page ...

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STV82x7 Bit Name Reset LS_C_VOLUME_ 1001 LS 10 bits volume Center channel 8 MSB MSB[7:0] 1000 See Figure 19: Volume Control on page 36 LS_C_VOLUME_LSB Address: DDh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 ...

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Register List LS_SUB_VOLUME_LSB Address: DFh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. LS_SUB_ bits volume Subwoofer channel 2 LSB VOLUME_LSB[1:0] See Figure 19: Volume Control on page 36 The volume ...

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STV82x7 LS_SL_VOLUME_LSB Address: E1h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. LS_LS_VOLUME_ bits volume Left surround channel 2 LSB in independent mode bits Left and Right LSB[1:0] ...

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Register List Bit Name Reset LS_SR_VOLUME_ bits volume Right channel 8 MSB in independent mode bits surround Left and Right LSB[1:0] balance 2 LSB in differential mode. See Figure 19: Volume Control on page ...

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STV82x7 HP_L_VOLUME_MSB Address: E6h Type: R/W Bit 7 Bit 6 Bit Name Reset HP_L_VOLUME_ 1001 HP 10 bits volume Left channel 8 MSB in independent mode bits Left and Right volume 8 MSB[7:0] 1000 MSB in differential ...

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Register List HP_R_VOLUME_LSB Address: E9h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. HP_R_VOLUME_ bits volume Right channel 2 LSB in independent mode bits Left and Right balance ...

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STV82x7 SCART_L_VOLUME_LSB Address: EBh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. SCART_L_ 00 SCART 10 bits volume Left channel 2 LSB in independent mode or SCART10 bits Left and Right VOLUME_LSB[1:0] volume 2 ...

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Register List Bit Name Reset SCART_R_ 00 SCART 10 bits volume Right channel 2 LSB in independent mode or SCART10 bits Left and Right VOLUME_LSB[1:0] balance 2 LSB in differential mode. See Figure 19: Volume Control on page 36 12.19 ...

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STV82x7 BEEPER_FREQ_VOL Address: F0h Type: R/W Bit 7 Bit 6 BEEP_FREQ[2:0] Bit Name Reset BEEP_FREQ[2:0] 011 Defines the frequency of the beeper tone from 62 kHz in octaves 000: 62.5 Hz 001: 125 Hz 010: 250 Hz ...

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Register List Bit Name Reset 1 LS Center digital soft mute C_D_MUTE 0: signal un-muted 1: signal muted 1 LS left/right digital soft mute LS_D_MUTE 0: signal un-muted 1: signal muted 12.21 S/PDIF S/PDIF_OUT_CONFIG Address: F2h Type: R/W Bit 7 ...

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STV82x7 Bit Name Reset HP_FORCE 0 1: force output of the HP signal (bypass surround when HP is detected and active, LS are not muted HP_LS_MUTE 1: when HP is detected and active, LS are muted 1 0: ...

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Register List SPDIF_CHANNEL_STATUS Address: F9h Type: R/W Bit 7 Bit 6 CHANNEL_STATUS Bit Name Reset Channel status mode: CHANNEL_STATUS[7:6] 00 00: Mode zero other values: reserved EMPHASIS[5:3] 000 Emphasis: according to IEC60958 specification Copyright: COPYRIGHT 0 0: Asserted 1: Not ...

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STV82x7 AUTOSTD_COEFF_INDEX_MSB Address: FCh Type: R/W Bit 7 Bit Bit Name Reset Bits [7:2] 0000000 Reserved. AUTOSTD_COEFF 0 FIR Coefficients table index (MSB) _INDEX_MSB AUTOSTD_COEFF_INDEX_LSB Address: FDh Type: R/W Bit 7 Bit 6 Bit Name Reset AUTOSTD_COEFF ...

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Electrical Characteristics 13 Electrical Characteristics Test Conditions: T OPER default register values for synthesizer, otherwise specified. 13.1 Absolute Maximum Ratings Symbol Analog and Digital 1.8 V Supply Voltage V XX_18 ( CC18_CLK1 CC18_CLK2 Analog and Digital 3.3 V ...

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STV82x7 13.4 Crystal Oscillator Symbol f Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor) P DF/F Frequency Tolerance at 25 °C P DF/F Frequency Stability versus Temperature within a range from °C ...

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Electrical Characteristics Symbol Parameter DFSIF SIF Carrier Accuracy for AM/QPSK Carrier Ratio for NICAM System AM/QPSK AGC AGC IF AGC Step step AGC Relative maximum gain to step 0 dyn 13.6 SIF to I²S Output Path Characteristics ...

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STV82x7 Symbol Parameter Clipping input level from SCART input Clipping CLIP SCART SCART Clipping input level from MONO_IN input THD from SCART input 1 V THD THD SCART SCART THD from MONO_IN input SCART input Signal to Noise SNR SCART ...

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Electrical Characteristics Symbol Parameter THD Total Harmonic Distortion DAC SNR Signal to Noise Ratio DAC V MAIN Output Amplitude OUTAMPDAC XTALK Left Right Crosstalk DAC 13.10 I²S to SCART Path Characteristics Test Conditions: Sampling Frequency = 32KHz prescale ...

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STV82x7 13.13 I²C Bus Characteristics Symbol Parameter SCL V Low Level Input Voltage IL V High Level Input Voltage IH I Input Leakage Current IL f Clock Frequency SCL t Input Rise Time R t Input Fall Time F C ...

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Electrical Characteristics SDA t BUF SCL t HD,STA SDA 2 13. Bus Interface 2 See timing for page Symbol Parameter I²S Input 2 V Input I S Low Level Voltage I2S_IL V 2 Input I ...

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STV82x7 Symbol Parameter Serial Clock Output f I2S_OSCl Frequency Serial Clock Output Ratio I2S_SCL Output Delay After Falling t S_De I2 l Edge of Clock 2 I S_SCLK 2 I ...

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Input/Output Groups 14 Input/Output Groups Pin numbers apply to SDIP package only. VCC18_IF SIF_P73 50K GND_PSUB VCC33_LS LS_L 25 SCR_FLT 26 LS_C 27 LS_L 28 LS_R 29 LS_SUB 30 HP_LSS_L 31 HP_LSS_R 32 GND_PSUB VCC18_IF SIF_N 74 GNDIF 140/149 SC1_OUTL ...

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STV82x7 VCC33_LS VREFA 11 GND33_LS VDD33_I01 HP_DET 35 ADR_SEL 36 RST_N 43 CLK_TST_CTRL 48 VSS VDD33_I02 BUS_EXD 68 IRQ 69 VSS VB G (1.2V 5K4 16K8 VDD33_I02 S/PDIF_IN Input/Output Groups VCC33_LS 10K 13 BAND-GAP=1.2V GND33_LS VDD33_I01 VDD33_I01 S/PDIF_OUT ...

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Input/Output Groups VDD33_I02 I2S_PCM_CLK 60 I2S_LR_CLK 61 I2S_DATA0 62 I2S_DATA1 63 I2S_DATA2 64 VSS SCL 35 SDA 40 VSS 142/149 VDD18 CLK_SEL 51 VSS VCC18_CLK1 XTALIN_CLKXTP 52 GND18_CLK1 VCC18_CLK1 XTALOUT_CLKXTM 53 GND18_CLK1 STV82x7 500K ...

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STV82x7 VDD33_I02 VCC18_CLK2 VCC18_CLK1 VDD33_I01 VDD18 VSS GND18_CLK1 GND18_CLK2 GND_PSUB Input/Output Groups 143/149 ...

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Input/Output Groups VDD18_CONV 34 22 VDD33_CONV 20 VCC_NISO VCC33_LS 16 7 VCC33_SC 3 VCC_H VDD18_ADC 71 76 VCC18_IF GND18_IF 77 GNDPW_IF 75 72 VSS18_ADC GND_PSUB 70 21 GND33_LS 17 GND_H 4 GND33_SC 8 GND_SA 12 VSS18_CONV 33 144/149 STV82x7 ...

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STV82x7 15 Package Mechanical Data Figure 30: 80-Pin Thin Plastic Quad Flat Package Dim. Min 0.05 A2 1.35 b 0. 0° Table 31: Package Mechanical ...

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Revision History 16 Revision History Revision Date 1.96 April 2004 1.97 April 2004 1.98 April 2004 1.99 June 2004 2.0 June 2004 2.01 July 2004 2.02 July 2004 2.03 January 2005 3 February 2005 146/149 Modification Preliminary Datasheet - First ...

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STV82x7 A Analog-to-Digital Conversion ............................. 21 Audio Matrix Analog .......................................................... 39 Automatic Frequency Control ............................ 23 Automatic Gain Control ...................................... 21 Automatic Overmodulation Detection ................ 22 Automatic Standard Recognition System .... 22 Back-end Processing ......................................... 24 Bass-Treble Control ...

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S SIF Signal Analog .......................................................... 21 Signal Processor Dedicated Digital .......................................... 24 Signal to Noise ................................................ 134 Smart Volume Control ....................................... 34 Soft Mute Control ............................................... 37 Software Information ........................................... 9 SRS TruBass ....................................................... 34 TruSurround ................................................. 33 WOW ........................................................... ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com ...