M58CR032C100ZB6T STMicroelectronics, M58CR032C100ZB6T Datasheet
M58CR032C100ZB6T
Available stocks
Related parts for M58CR032C100ZB6T
M58CR032C100ZB6T Summary of contents
Page 1
FEATURES SUMMARY SUPPLY VOLTAGE – 1.65V to 2V for Program, Erase and DD Read – 1.65V to 3.3V for I/O Buffers DDQ – 12V for fast Program (optional) PP SYNCHRONOUS / ASYNCHRONOUS READ – ...
Page 2
M58CR032C, M58CR032D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Wrap Burst Bit (M3 ...
Page 4
M58CR032C, M58CR032D Program Status (Bit ...
Page 5
Table 34. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
M58CR032C, M58CR032D SUMMARY DESCRIPTION The M58CR032 Mbit (2Mbit x16) non-vola- tile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.0V V supply for the ...
Page 7
Figure 2. Logic Diagram DDQ A0-A20 W E M58CR032C G M58CR032D Table 1. Signal Names A0-A20 DQ0-DQ15 DQ0-DQ15 W RP WAIT WAIT ...
Page 8
M58CR032C, M58CR032D Figure 3. TFBGA Connections (Top view through package A11 B A12 C A13 D A15 E V DDQ DQ7 Table 2. Bank Architecture Bank A Bank B 8/ ...
Page 9
Figure 4. Memory Map Top Boot Block Address lines A20-A0 000000h 512 Kbit or 32 KWord 007FFFh Bank B 178000h 512 Kbit or 32 KWord 17FFFFh 180000h 512 Kbit or 32 KWord 187FFFh 1F0000h 512 Kbit or 32 KWord 1F7FFFh ...
Page 10
M58CR032C, M58CR032D SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to ...
Page 11
V > V enables these functions (see Ta- PP PP1 ble 19, DC Characteristics for the relevant values only sampled at the beginning of a program PP or erase; a change in its value after the operation ...
Page 12
M58CR032C, M58CR032D BUS OPERATIONS There are two types of bus operations that control the device: Asynchronous (Read, Page Read, Write, Output Disable, Standby, Automatic Stand- by and Reset/Power-Down) and Synchronous (Synchronous Read and Synchronous Burst Read). The Dual Bank architecture ...
Page 13
Protection Register, see Figure 6, for an example of a single synchronous read operation. Synchronous Burst Read. The device also sup- ports a synchronous burst read. In this mode a burst sequence is started at the first clock edge (rising ...
Page 14
M58CR032C, M58CR032D Figure 6. Synchronous Single Read Operation K L A20-A0 VALID ADDRESS DQ15-DQ0 DQ15-DQ0 DQ15-DQ0 14/63 X latency = 2 VALID DATA X latency = 3 X latency = 4 NOT VALID NOT VALID NOT VALID VALID DATA NOT ...
Page 15
Burst Configuration Register The Burst Configuration Register is used to config- ure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface. After a Reset or Power- Up the device ...
Page 16
M58CR032C, M58CR032D be asserted only once during a continuous burst access. See also Table 5, Burst Type Definition. Table 4. Burst Configuration Register Bit Description M15 Read Select M14 (2) M13-M11 X-Latency (3) M10 Power-Down M9 M8 Wait M7 Burst ...
Page 17
Table 5. Burst Type Definition Start Address 4 Words Sequential 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1-2 ... 7 7-4-5-6 ... Sequential 0 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5-6 ... 7 7-8-9-10 ... 60 ...
Page 18
M58CR032C, M58CR032D Figure 7. X-Latency Configuration Sequence K L A20-A0 VALID ADDRESS DQ15-DQ0 DQ15-DQ0 DQ15-DQ0 Figure 8. Wait Configuration Sequence A20-A0 VALID ADDRESS DQ15-DQ0 WAIT M8 = '0' WAIT M8 = '1' 18/63 X latency = ...
Page 19
COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution ...
Page 20
M58CR032C, M58CR032D gram/Erase Controller does it automatically before erasing. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. The second latches the block address in the internal state machine and ...
Page 21
Read operations in the bank being programmed output the Status Register content after the pro- gramming has started. During Double Word Program operations the bank being programmed will only accept the Read Sta- tus Register command and the Program/Erase Suspend ...
Page 22
M58CR032C, M58CR032D Protection Register Program Command The Protection Register Program command is used to Program the 64 bit user One-Time-Pro- grammable (OTP) segment of the Protection Reg- ister. The segment is programmed 16 bits at a time. When shipped all ...
Page 23
The value for the Burst Configuration Register is always presented on A0-A15 A0 A1, etc.; the other address bits are ignored. Table 6. Commands Commands 1st Cycle Op. Add Data Op. Read Memory 1+ Write ...
Page 24
M58CR032C, M58CR032D Table 7. Dual Bank Operations Status of one Read bank Array Status Idle Yes Reading – Programming Yes Erasing Yes Program Yes Suspended Erase Yes Suspended Note: 1. For detailed description of command see Table 6, 36 and ...
Page 25
Table 10. Read Protection Register Word A20-16 A15-8 Lock Unique Unique Unique ...
Page 26
M58CR032C, M58CR032D Table 12. Program, Erase Times and Program, Erase Endurance Cycles Parameter Parameter Block (4 KWord) Erase Main Block (32 KWord) Erase Bank A (8Mbit) Erase Bank B (24Mbit) Erase Parameter Block (4 KWord) Program Main Block (32 KWord) ...
Page 27
BLOCK LOCKING The M58CR032 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software- only control ...
Page 28
M58CR032C, M58CR032D Table 13. Block Lock Status Item Block Lock Configuration Block is Unlocked Block is Locked Block is Locked-Down Table 14. Lock Status Current (1) Protection Status (WP, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 ...
Page 29
STATUS REGISTER The M58CR032 has two Status Registers, one for each bank. The Status Registers provide informa- tion on the current or previous Program or Erase operations executed in each bank. The various bits convey information and errors on the ...
Page 30
M58CR032C, M58CR032D been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within ...
Page 31
... Note: 1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. ...
Page 32
M58CR032C, M58CR032D DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...
Page 33
Table 19. DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) I DD1 Supply Current Synchronous Read (f=40MHz) Supply Current I DD2 (Reset) I Supply Current (Standby) DD3 ...
Page 34
M58CR032C, M58CR032D Table 20. DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 Program Voltage ...
Page 35
Figure 11. Asynchronous Read AC Waveforms M58CR032C, M58CR032D 35/63 ...
Page 36
M58CR032C, M58CR032D Figure 12. Asynchronous Page Read AC Waveforms 36/63 ...
Page 37
Table 21. Asynchronous Read AC Characteristics Symbol Alt Parameter Address Valid to Next t t AVAV RC Address Valid Address valid to Latch t t AVLH AVAVDH Enable High Address Valid to Output t t AVQV ACC Valid (Random) Address ...
Page 38
M58CR032C, M58CR032D Figure 13. Synchronous Burst Read 38/63 ...
Page 39
Table 22. Synchronous Burst Read AC Characteristics Symbol Alt Parameter Address Valid to Clock t t AVKH AVCLKH High Chip Enable Low to Clock t t ELKH CELCLKH High t t Clock Period KHKH CLK Clock High to Address t ...
Page 40
M58CR032C, M58CR032D Figure 14. Write AC Waveforms, Write Enable Controlled 40/63 ...
Page 41
Table 23. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH t t Input Valid to Write Enable High DVWH DS t Chip ...
Page 42
M58CR032C, M58CR032D Figure 15. Write AC Waveforms, Chip Enable Controlled 42/63 ...
Page 43
Table 24. Write AC Characteristics, Chip Enable Controlled Symbol Alt Parameter t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH t t Input Valid to Chip Enable High DVEH DS t ...
Page 44
M58CR032C, M58CR032D Figure 16. Reset and Power-up AC Waveforms tVDHPH VDD, VDDQ Table 25. Reset and Power-up AC Characteristics Symbol Parameter (1,2) RP Pulse Width t PLPH t PLWL t Reset Low to Device Enabled PLEL ...
Page 45
PACKAGE MECHANICAL Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline BALL "A1" A Note: Drawing is not to scale. Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm ...
Page 46
M58CR032C, M58CR032D PART NUMBERING Table 27. Ordering Information Scheme Example: Device Type M58 Architecture C = Dual Bank, Burst Mode Operating Voltage 1.65V to 2.0V 1.65V to 3.3V DD DDQ Device Function 032C = ...
Page 47
REVISION HISTORY Table 28. Document Revision History Date Version April 2001 -01 23-OCT-2001 -02 21-Mar-2002 -03 06-Sep-2002 3.1 Revision Details First Issue 85ns speed class added, document classified as Preliminary Data Document completely revised. Changes in CFI content, Program and ...
Page 48
M58CR032C, M58CR032D APPENDIX A. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various ...
Page 49
Table 31. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0017h V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0020h V [Programming] Supply Minimum Program/Erase voltage PP 1Dh 0017h ...
Page 50
M58CR032C, M58CR032D Offset Word Data Mode 2Dh 003Eh Region 1 Information 2Eh 0000h Number of identical-size erase block = 003Eh+1 2Fh 0000h Region 1 Information 30h 0001h Block size in Region 1 = 0100h * 256 Bytes 31h 0007h Region ...
Page 51
Data Offset (P+9)h = 42h 0001h Supported Functions after Suspend Read Array, Read Status Register and CFI Query bit 0 bit (P+A)h = 43h 0003h Block Protect Status Defines which bits in the Block Status Register section ...
Page 52
M58CR032C, M58CR032D Data Offset (P+19)h = 52h 0001h Supported handshaking signal (WAIT pin) bit 0 bit 1 Table 35. Security Code Area Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h 52/63 Description during Synchronous Read during Asynchronous Read ...
Page 53
APPENDIX B. FLOWCHARTS AND PSEUDO CODES Figure 18. Program Flowchart and Pseudo Code Start Write 40h or 10h Write Address & Data Read Status Register YES YES YES ...
Page 54
M58CR032C, M58CR032D Figure 19. Double Word Program Flowchart and Pseudo code Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Read Status Register YES ...
Page 55
Figure 20. Quadruple Word Program Flowchart and Pseudo Code Start Write 55h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) ...
Page 56
M58CR032C, M58CR032D Figure 21. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues 56/63 ...
Page 57
Figure 22. Block Erase Flowchart and Pseudo Code Start Write 20h Write Block Address & D0h Read Status Register YES YES YES b4 YES ...
Page 58
M58CR032C, M58CR032D Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block ...
Page 59
Figure 24. Locking Operations Flowchart and Pseudo Code Start Write 60h Write 01h, D0h or 2Fh Write 90h Read Block Lock States Locking change confirmed? YES Write FFh End locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; /*configuration setup*/ if ...
Page 60
M58CR032C, M58CR032D Figure 25. Protection Register Program Flowchart and Pseudo Code Start Write C0h Write Address & Data Read Status Register YES YES YES NO Program to Protected ...
Page 61
APPENDIX C. COMMAND INTERFACE STATE TABLES Table 36. Command Interface States - Lock table Current State of the Current Bank Current State of Other Mode State Others Bank Array CFI SEE Any State Read MODIFY Read Array Read Array Electronic ...
Page 62
M58CR032C, M58CR032D Table 37. Command Interface States - Modify Table Current State of the Current Bank Current State of the Other Bank Mode State Setup Busy Array, CFI, Idle Electronic Read Signature, Erase Suspend Status Register Program Suspend Setup Busy ...
Page 63
... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...