PGH758AM STMicroelectronics, PGH758AM Datasheet
PGH758AM
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PGH758AM Summary of contents
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SUPPLY VOLTAGE – 1.65V to 2.0V for Program, DD DDQ Erase and Read – 12V for fast Program (optional) PP MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ – Configurable Burst mode Read – Page mode ...
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M59MR032C, M59MR032D Figure 2. LFBGA Connections (Top view through package WAIT F V DDQ A16 ADQ7 H ADQ15 ADQ14 ...
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Figure 3. µBGA Connections (Top view through package WAIT D V DDQ ADQ7 F ADQ15 ADQ14 ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi- tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual- ity documents. ...
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Organization The M59MR032 is organized as 2Mbit by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A20 are the MSB addresses. Memory control is ...
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M59MR032C, M59MR032D Table 4. Bank A, Top Boot Block Addresses M59MR032C Size # Address Range (KWord 1FF000h-1FFFFFh 21 4 1FE000h-1FEFFFh 20 4 1FD000h-1FDFFFh 19 4 1FC000h-1FCFFFh 18 4 1FB000h-1FBFFFh 17 4 1FA000h-1FAFFFh 16 4 1F9000h-1F9FFFh 15 4 1F8000h-1F8FFFh ...
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Table 6. Bank B, Bottom Boot Block Addresses M59MR032D Size # Address Range (KWord 1F8000h-1FFFFFh 46 32 1F0000h-1F7FFFh 45 32 1E8000h-1EFFFFh 44 32 1E0000h-1E7FFFh 43 32 1D8000h-1DFFFFh 42 32 1D0000h-1D7FFFh 41 32 1C8000h-1CFFFFh 40 32 1C0000h-1C7FFFh 39 32 ...
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M59MR032C, M59MR032D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0- ADQ15). When Chip Enable put Enable the multiplexed address/ IH data bus is used to input ...
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Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage ...
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M59MR032C, M59MR032D DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Address Latch, Read Array (Random, and Page Modes), Write com- mand, Output Disable, Standby, Reset/Power- down and Block Locking. See Table 8. Address Latch. In ...
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Figure 4. Read Operation Sequence when CR15 = 0 (excluding Read Memory Array A16-A20 VALID ADDRESS ADQ0-ADQ15 VALID ADDRESS ADQ0-ADQ15 VALID ADDRESS ADQ0-ADQ15 VALID ADDRESS Burst Read. The device also supports a burst read. In this mode, an ...
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M59MR032C, M59MR032D INSTRUCTIONS AND COMMANDS Seventeen instructions are defined (see Table 17), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Poll- ing, Toggle, Error bits can be read ...
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Auto Select (AS) Instruction. This instruc- tion uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the ...
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M59MR032C, M59MR032D Table 13. X-Latency Configuration Configuration Code (1) 5 (1) 6 Note: 1. Configuration codes 5 and 6 may be used only in conjunction with configuration bit CR9 set at “1” (one data every 2 clock ...
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Table 15. Burst Order and Length Configuration 4 Words Starting Address Linear 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1-2 ... 7 7-4-5-6 ... – X-Latency (CR13-CR11). These configuration bits define the number of clock cycles ...
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M59MR032C, M59MR032D (1) Table 16. Protection States (2) Current State Program/Erase (WP, ADQ1, Allowed ADQ0) 100 yes 101 no 110 yes 111 no 000 yes 001 no 011 no Note: 1. All blocks are protected at power-up, so the default ...
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for at least t IL protection and lock status can be monitored for each block using the Autoselect (AS) instruc- tion. Protected blocks ...
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M59MR032C, M59MR032D (1,2) Table 17. Instructions Mne. Instr. Cyc. 1+ Read/Reset (4) RD Memory Array 3+ RCFI CFI Query 1+ (4) Auto Select 3+ AS Configuration CR 4 Register Write PG Program 4 Double Word DPG 5 Program Enter Bypass ...
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Mne. Instr. Cyc. BL Block Lock 4 BE Block Erase 6+ BKE Bank Erase 6 ES Erase Suspend 1 ER Erase Resume 1 Note: 1. Commands not interpreted in this table will default to read array mode. 2. For Coded ...
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M59MR032C, M59MR032D STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on ADQ7, detection of Toggle on ADQ6 and ADQ2, or Error on ADQ5 bits. Any read at- tempt within the Bank being modified and during Program ...
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Table 18. Status Register Bits Program Block Erase Timeout Block/Chip Erase In Progress Erase Suspend Mode Programming during Erase Suspend Word Program Successfully/ Completed Block/Chip Erase Word Program Exceeded Block/Chip Erase Time Limit Program in Suspend Note: 1. Status Register ...
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M59MR032C, M59MR032D COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine ...
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Table 21. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0017h V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0022h V [Programming] Supply Minimum Program/Erase voltage PP 1Dh 0017h ...
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M59MR032C, M59MR032D Table 22. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description: Asynchronous x16 29h 0000h 2Ah 0000h Maximum number of bytes in multi-byte program or page = ...
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Table 23. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 39h 0050h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” 0049h (P+3)h = 3Ch 0031h Major version number, ASCII (P+4)h = 3Dh 0030h Minor version number, ASCII ...
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M59MR032C, M59MR032D Table 24. Burst Read Information Offset Data (P+F)h = 48h 0003h Page-mode read capability (P+10)h = 49h 0003h Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+11)h = 4Ah 0001h Synchronous mode ...
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Table 26. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 6. Testing Input/Output Waveforms V DDQ 0V (1) Table 27. Capacitance ( ° MHz) A ...
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M59MR032C, M59MR032D Table 28. DC Characteristics (T = –40 to 85° DDQ Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current (Asynchronous Read Mode) I CC1 Supply Current (Synchronous Read ...
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Table 29. Asynchronous Read AC Characteristics (T = –40 to 85° DDQ Symbol Alt Address Valid to Next t t AVAV RC Address Valid Address valid to Latch t t AVLH AVAVDH Enable High Address ...
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M59MR032C, M59MR032D Figure 8. Asynchronous Read AC Waveforms 30/49 ...
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Figure 9. Page Read AC Waveforms M59MR032C, M59MR032D 31/49 ...
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M59MR032C, M59MR032D Table 30. Synchronous Burst Read AC Characteristics (T = –40 to 85° DDQ Symbol Alt t t Address Valid to Clock AVK AVCLKH t t Chip Enable Low to Clock ELK CELCLKH t ...
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Figure 10. Synchronous Burst Read M59MR032C, M59MR032D 33/49 ...
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M59MR032C, M59MR032D Figure 11. Synchronous Burst Read (with Data Hold Configuration bit CR9 = 1) 34/49 ...
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Table 31. Write AC Characteristics, Write Enable Controlled (T = – ° DDQ Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH ...
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M59MR032C, M59MR032D Figure 12. Write AC Waveforms, W Controlled 36/49 ...
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Table 32. Write AC Characteristics, Chip Enable Controlled (T = – ° DDQ Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH ...
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M59MR032C, M59MR032D Figure 13. Write AC Waveforms, E Controlled 38/49 ...
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Table 33. Read and Write AC Characteristic, RP Related (T = –40 to 85° DDQ Symbol Alt RP High to Data Valid t PHQ7V1 (Read Mode) RP High to Data Valid t PHQ7V2 (Power-down enabled) ...
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M59MR032C, M59MR032D Table 34. Program, Erase Times and Program, Erase Endurance Cycles ( 70° 1.65V to 2.0V DDQ Parameter Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase ...
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Figure 15. Data Polling ADQ7 AC Waveforms (when Configuration Register bit CR15 = 1) M59MR032C, M59MR032D 41/49 ...
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M59MR032C, M59MR032D Figure 16. Data Toggle DQ6, DQ2 AC Waveforms (when Configuration Register bit CR15 = 1) 42/49 ...
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Figure 17. Data Polling Flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL Figure 18. Data Toggle Flowchart PASS AI90125 M59MR032C, M59MR032D ...
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... Table 37. Daisy Chain Ordering Scheme Example: Device Type M59MR032 Daisy Chain -GC = µBGA46: 0.5 mm pitch Option T = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the STMicroelectronics Sales Office nearest to you. 44/49 M59MR032C 100 GC 6 M59MR032 - ...
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Table 38. Revision History Date Version July 1999 -01 First Issue FBGA Connections change FBGA Package Mechanical Data and Outline change 12/01/99 -02 FBGA Daisy Chain diagrams added µBGA Package added Document type: from Product Preview to Preliminary Data Bus ...
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M59MR032C, M59MR032D Table 39. LFBGA54 - ball array, 0.5 mm pitch, Package Mechanical Data Symbol Typ A 1.100 A1 0.150 A2 0.950 b 0.400 D 7.000 D1 4.500 ddd e 0.500 E 12.000 E1 1.500 E2 6.500 ...
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Table 40. µBGA46 - ball array, 0.5 mm pitch, Package Mechanical Data Symbol Typ 0.700 b 0.320 D 10.530 D1 4.500 D2 6.500 D3 8.500 ddd e 0.500 E 6.290 E1 1.500 E2 3.500 ...
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M59MR032C, M59MR032D Figure 21. µBGA46 Daisy Chain - Package Connections (Top view through package Figure 22. µBGA46 Daisy Chain - PCB Connections proposal (Top view through package ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...