TDA6650TT/C3 NXP Semiconductors, TDA6650TT/C3 Datasheet
TDA6650TT/C3
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TDA6650TT/C3 Summary of contents
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... Recommended band limits in MHz RF input Min Max 44.25 157.25 157.25 443.25 443.25 863.25 47.00 160.00 160.00 446.00 446.00 866.00 CCA Product data sheet Type version TDA6650TT/C3 TDA6651TT/C3 TDA6650TT/C3/S2 TDA6651TT/C3/S2 TDA6651TT/C3/S3 Oscillator Min [1] 83.15 196.15 482.15 [2] 83.15 196.15 482.15 . [1] Max 196.15 482.15 902.15 196.15 482.15 902.15 ...
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... NXP Semiconductors Five open-drain PMOS ports are included on the IC. Two of them, BS1 and BS2, are also dedicated to the selection of the low, mid and high bands. PMOS port BS5 pin is shared with the ADC. The AGC detector provides a control that can be used in a tuner to set the gain of the RF stage ...
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... Digital set-top boxes. 4. Ordering information Table 3. Ordering information Type number Package Name TDA6650TT/C3 TSSOP38 TDA6650TT/C3/S2 TDA6651TT/C3 TDA6651TT/C3/S2 TDA6651TT/C3/S3 TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer Description plastic thin shrink small outline package; 38 leads; body width 4.4 mm; ...
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... NXP Semiconductors 5. Block diagram n.c. 21 (18) TDA6650TT (TDA6651TT) 4 (35) LOW LBIN INPUT 3 (36) MID MBIN INPUT 1 (38) HBIN1 HIGH 2 (37) INPUT HBIN2 5 (34) RFGND 24 (15) V CCD FRACTIONAL DIVIDER 19 (20) XTAL1 CRYSTAL 20 (19) OSCILLATOR XTAL2 15 (24) SCL 16 (23) 2 SDA I C-BUS 17 (22) TRANSCEIVER AS 13 (26) ...
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... NXP Semiconductors 6. Pinning information 6.1 Pin description Table 4. Symbol HBIN1 HBIN2 MBIN LBIN RFGND IFFIL1 IFFIL2 BS4 AGC BS3 BS2 BS1 BVS ADC/BS5 SCL SDA AS XTOUT XTAL1 XTAL2 n CCD PLLGND V CCA IFOUTB IFOUTA IFGND HOSCIN1 HOSCOUT1 HOSCOUT2 HOSCIN2 TDA6650TT_6651TT_5 Product data sheet TDA6650TT ...
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... NXP Semiconductors Table 4. Symbol MOSCIN1 MOSCIN2 OSCGND LOSCOUT LOSCIN 6.2 Pinning HBIN1 1 HBIN2 2 MBIN 3 4 LBIN RFGND 5 IFFIL1 6 7 IFFIL2 8 BS4 AGC 9 TDA6650TT BS3 10 11 BS2 BS1 12 BVS 13 14 ADC/BS5 15 SCL SDA XTOUT XTAL1 19 Fig 2. Pin configuration TDA6650TT 7. Functional description 7 ...
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... NXP Semiconductors the reference divider ratio, depending on the step frequency selected. The crystal oscillator requires a 4 MHz crystal in series with capacitor between pins XTAL1 and XTAL2. The output of the phase comparator drives the charge pump and the loop amplifier section. This amplifi ...
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... NXP Semiconductors Linked to this noise improvement, some disturbances may become visible while they were not visible because they were hidden into the noise in analog dedicated applications and circuits. This is especially true for disturbances coming from the I is intended for the MOPLL or for another slave on the bus. ...
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... NXP Semiconductors ADDRESS DIVIDER START BYTE BYTE 1 2 Fig 4. Example of I C-bus transmission frame 2 Table 6. I C-bus write data format Name Byte Address byte 1 Divider byte 1 (DB1) 2 Divider byte 2 (DB2) 3 Control byte 1 (CB1); 4 see Table 7 Control byte 2 (CB2) 5 [1] MSB is transmitted first. ...
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... NXP Semiconductors 2 8.1.1 I C-bus address selection The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four MOPLL ICs in one system. between the voltage applied to the AS input and the MA1 and MA0 bits. Table 8. Voltage applied to pin ...
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... NXP Semiconductors Table 10 8.1.4 AGC detector setting The AGC take-over point can be selected out of 6 levels according to Table 11. AL2 [1] This take-over point is available for both symmetrical and asymmetrical modes. [2] This take-over point is available for asymmetrical mode only. ...
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... NXP Semiconductors Table 12. CP2 8.1.6 Automatic Loop Bandwidth Control (ALBC PLL controlled VCO in which the PLL reduces phase noise close to the carrier, there is an optimum loop bandwidth corresponding to the minimum integrated phase jitter. This loop bandwidth depends on different parameters like the VCO slope, the loop filter components, the dividing ratio and the gain of the phase detector and charge pump ...
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... NXP Semiconductors Table 14. LO frequency 184 MHz to 196 MHz 196 MHz to 224 MHz 224 MHz to 296 MHz 296 MHz to 380 MHz 380 MHz to 404 MHz 404 MHz to 448 MHz 448 MHz to 472 MHz 472 MHz to 484 MHz 484 MHz to 604 MHz ...
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... NXP Semiconductors Table 16. Bit ALBC AGC A2, A1, A0 Table 17. Voltage applied to pin ADC 0.6V CC 0.45V CC 0.3V CC 0.15V 0.15V [1] Accuracy is 0.03V uses the same pin as the ADC and can not be used when the ADC is in use. 8.3 Status at power-on reset At power on or when the supply voltage drops below approximately 2.85 V (at ...
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... NXP Semiconductors 9. Internal circuitry Table 19. Internal pin configuration Symbol Pin TDA6650TT TDA6651TT HBIN1 1 38 HBIN2 2 37 MBIN 3 36 LBIN 4 35 RFGND 5 34 IFFIL1 6 33 IFFIL2 7 32 BS4 8 31 TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer ...
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... NXP Semiconductors Table 19. Internal pin configuration Symbol Pin TDA6650TT TDA6651TT AGC 9 30 BS3 10 29 BS2 11 28 BS1 12 27 BVS 13 26 ADC/BS5 14 25 TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer …continued Average DC voltage versus band ...
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... NXP Semiconductors Table 19. Internal pin configuration Symbol Pin TDA6650TT TDA6651TT SCL 15 24 SDA XTOUT 18 21 XTAL1 19 20 XTAL2 TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer …continued Average DC voltage versus band ...
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... NXP Semiconductors Table 19. Internal pin configuration Symbol Pin TDA6650TT TDA6651TT CCD PLLGND CCA IFOUTB 27 12 IFOUTA 28 11 IFGND 29 10 HOSCIN1 30 9 HOSCOUT1 31 8 HOSCOUT2 32 7 HOSCIN2 33 6 TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer … ...
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... NXP Semiconductors Table 19. Internal pin configuration Symbol Pin TDA6650TT TDA6651TT MOSCIN1 34 5 MOSCIN2 35 4 OSCGND 36 3 LOSCOUT 37 2 LOSCIN 38 1 [1] The pin numbers in parenthesis refer to the TDA6651TT. 10. Limiting values Table 20. In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are entering the IC and negative currents are going out of the IC ...
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... NXP Semiconductors Table 20. In accordance with the Absolute Maximum Rating System (IEC 60134). Positive currents are entering the IC and negative currents are going out of the IC; all voltages are referenced to ground [1] . Symbol BSn I BS(tot) t sc(max) T stg T amb T j [1] Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. ...
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... NXP Semiconductors 12. Characteristics Table 22. Characteristics values are given for an asymmetrical IF output loaded with a 75 CCA CCD amb symmetrical IF output loaded with 1. positive currents are entering the IC and negative currents are going out of the IC; the performances of the circuits are measured in the measurement circuits ...
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... V tuning supply voltage = integrated between 1 kHz and 1 MHz offset from the carrier digital only application: TDA6650TT/C3/S2; TDA6651TT/C3/S2; TDA6651TT/C3/S3 hybrid application: TDA6650TT/C3; TDA6651TT/C3 picture carrier for digital only application: TDA6650TT/C3/S2; TDA6651TT/C3/S2; TDA6651TT/C3/S3 picture carrier for hybrid application: TDA6650TT/C3; TDA6651TT/C3 Rev. 05 — ...
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... MHz RF asymmetrical application; see f = 44.25 MHz 157.25 MHz RF symmetrical application; see f = 44.25 MHz 157.25 MHz RF asymmetrical IF output hybrid application: TDA6650TT/C3; TDA6651TT/C3 RFpix see Figure 44.25 MHz; see Figure 157.25 MHz; see Figure 44.25 MHz to 157.25 MHz; RF see ...
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... RF(unwanted) asymmetrical IF output see Figure 25 see Figure 6 see Figure 6 picture carrier for digital only application: TDA6650TT/C3/S2; TDA6651TT/C3/S2; TDA6651TT/C3/S3 picture carrier for hybrid application: TDA6650TT/C3; TDA6651TT/C3 asymmetrical IF output; load = 75 ; see Figure 443.25 MHz 863.25 MHz RF symmetrical IF output; load = 1. see Figure 443 ...
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... MHz; see Figure 863.25 MHz; see Figure with compensation CC TDA6650TT/C3/S2; TDA6651TT/C3/S2; TDA6651TT/C3/S3 1 kHz frequency offset; f comp see Figure 8, 27 and 28 10 kHz frequency offset; worst case in the frequency range; see Figure 9, 27 and 28 100 kHz frequency offset ...
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... Figure 10, 27 and 28 1.4 MHz frequency offset; worst case in the frequency range; see Figure 27 TDA6650TT/C3; TDA6651TT/C3 1 kHz frequency offset; f comp see Figure 11, 29, and 30 10 kHz frequency offset; worst case in the frequency range; see Figure ...
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... Figure 10, 27 and 28 1.4 MHz frequency offset; worst case in the frequency range; see Figure 27 TDA6650TT/C3; TDA6651TT/C3 1 kHz frequency offset; f comp see Figure 11, 29, and 30 10 kHz frequency offset; worst case in the frequency range; see Figure ...
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... IF = 38.9 MHz step [17] bits AL[2:0] = 000 maximum level TDA6650TT/C3; TDA6651TT/C3; TDA6650TT/C3/S2; TDA6651TT/C3/S2 TDA6651TT/C3/S3 minimum level bits AL[2:0] = 111 TDA6650TT/C3; TDA6651TT/C3; TDA6650TT/C3/S2; TDA6651TT/C3/S2 TDA6651TT/C3/S3 AGC bit = 0 or AGC not active AGC bit = 1 or AGC active bits AL[2:0] = 110 < V AGC , as defined in Section 10. ...
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... NXP Semiconductors [2] The drive level is expected with a 50 series resistance values. [3] The V level is measured when the pin XTOUT is loaded with parallel with 10 pF. XTOUT [4] The RF frequency range is defined by the oscillator frequency range and the Intermediate Frequency (IF). [5] The 1 % cross modulation performance is measured with AGC detector turned off (AGC bits set to 110). ...
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... NXP Semiconductors Fig 6. Input admittance ( the mid band mixer (100 MHz to 500 MHz Fig 7. Input impedance ( the high band mixer (400 MHz to 900 MHz TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer ...
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... NXP Semiconductors 80 osc (dBc/Hz 100 40 140 For measurement circuit see Fig 8. 1 kHz phase noise typical performance in digital application 80 osc (dBc/Hz 100 105 110 40 140 For measurement circuit see Fig 9. 10 kHz phase noise typical performance in digital application TDA6650TT_6651TT_5 Product data sheet TDA6650TT ...
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... NXP Semiconductors 100 osc (dBc/Hz) 105 110 115 120 40 140 For measurement circuit see Fig 10. 100 kHz phase noise typical performance in digital application 80 osc (dBc/Hz 100 105 40 140 For measurement circuit see Fig 11. 1 kHz phase noise typical performance in hybrid application ...
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... NXP Semiconductors 80 osc (dBc/Hz 100 105 40 140 For measurement circuit see Fig 12. 10 kHz phase noise typical performance in hybrid application 100 osc (dBc/Hz) 105 110 115 120 40 140 For measurement circuit see Fig 13. 100 kHz phase noise typical performance in hybrid application ...
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... NXP Semiconductors Fig 14. Gain (G Fig 15. Gain (G TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer signal source meas V i RMS voltmeter Z >> meas meas V = V’ + 3.75 dB. ...
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... NXP Semiconductors NOISE SOURCE loss of input circuit (dB). meas Fig 16. Noise figure (NF) measurement in low and mid band with asymmetrical IF output BNC Cs Cc connector Schematic 1 For MHz (Schematic 1) RF Loss = 0 dB parallel with a 0 trimmer parallel with a 0 trimmer. ...
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... NXP Semiconductors kHz 50 unwanted e u signal source 50 wanted e signal w source 3.75 dB. o meas Wanted signal source at f RFpix Unwanted output signal at f The level of unwanted signal is measured by causing 0 modulation in the wanted signal. Fig 18. Cross modulation measurement in low and mid band with asymmetrical IF output ...
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... NXP Semiconductors Fig 20. Gain ( Fig 21. Gain (G TDA6650TT_6651TT_5 Product data sheet TDA6650TT; TDA6651TT 5 V mixer/oscillator and low noise PLL synthesizer signal source 50 A HYBRID meas RMS voltmeter Loss in hybrid = 1 dB loss = meas V = V’ + 3.75 dB. ...
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... NXP Semiconductors NOISE SOURCE Loss in hybrid = 1 dB loss. meas Fig 22. Noise figure (NF) measurement in high band with asymmetrical IF output kHz unwanted signal e u source HYBRID wanted e signal w source Wanted signal source at f RFpix Unwanted output signal at f The level of unwanted signal is measured by causing 0 modulation in the wanted signal. ...
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... NXP Semiconductors Fig 25. Maximum RF input level without lock-out in low and mid band with asymmetrical Fig 26. Maximum RF input level without lock-out in high band with asymmetrical IF output 12.1 PLL loop stability of measurement circuit The TDA6650TT; TDA6651TT PLL loop stability is guaranteed in the configuration of Figure ...
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... NXP Semiconductors The delivered current can be simply calculated with the following formula: I delivered where: I delivered V is the supply source voltage or DC-to-DC converter output voltage the tuning voltage the pull-up resistor between the DC supply source (or the DC-to-DC converter pu output) and the tuning line (R19 the charge pump current in use ...
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LOW MID HIGH1 C4 C3 4 TOKO 500 C27 C26 AGC TP1 C28 150 nF D4 R20 ...
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LOW MID HIGH1 C4 C3 4 TOKO 500 C27 C26 AGC TP1 C28 150 nF D4 R20 ...
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J4 J3 LOW MID HIGH1 C4 C3 4 TOKO 500 C27 C26 AGC TP1 C28 150 nF D4 R20 R21 ...
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J4 J3 LOW MID HIGH1 C4 C3 4 TOKO 500 C27 C26 AGC TP1 C28 150 nF D4 R20 R21 ...
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... NXP Semiconductors 13. Application information 13.1 Tuning amplifier The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load which is connected to the tuning voltage supply rail. The loop filter design depends on the oscillator characteristics and the selected reference frequency as well as the required PLL loop bandwidth ...
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... NXP Semiconductors To fully program the device, either sequence of arrangements of the bytes are also possible. Table 23. Start Address S [1] Control byte 1 with bit T program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0. [2] Control byte 1 with bit T program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0 ...
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... NXP Semiconductors Table 29. Start S [1] Control byte 1 with bit T program AGC time constant bit ATC and AGC take-over point bits AL2, AL1 and AL0. Table 30. Start Address byte S C2 [1] Control byte 1 with bit T program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0 ...
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... NXP Semiconductors 14. Package outline TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 33. Acronym ADC AGC ALBC DVB C-bus IF LO LSB MOPLL MSB OFDM ...
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... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Table 3 “Ordering information” updated with type numbers TDA6650TT/C3/S2, DA6651TT/C3/S2 and TDA6651TT/C3/S3 Table 22 “Characteristics” condition of leakage current (I 0 < ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Application summary . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Mixer, Oscillator and PLL (MOPLL) functions 7.2 I C-bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 7.3 Phase noise, I C-bus traffic and crosstalk . . . . 7 ...