GS82032T-5 GSI Technology, GS82032T-5 Datasheet

GS82032T-5

Manufacturer Part Number

GS82032T-5

Description

100MHz 12ns 64K x 32 2M synchronous burst SRAM

Manufacturer

GSI Technology

Datasheet

1.GS82032T-5.pdf (23 pages)

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TQFP, QFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP or QFP package

Functional Description

Applications

The GS82032 is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Rev: 1.04 2/2001

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Through

Pipeline

3-1-1-1

2-1-1-1

operation

Flow

tCycle

-150 -138 -133 -117 -100

10.5

270

170

6.6

3.8

7.25

245

120

9.7

240

120

2M Synchronous Burst SRAM

7.5

, E

210

120

8.5

4.5

, E

180

120

), address burst

12.5

150

-66

64K x 32

1/23

Unit

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump

1F in the FP-BGA). Holding the FT mode pin/bump low,

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipeline mode, activating the rising-edge-triggered

Data Output Register.

SCD Pipelined Reads

The GS82032 is an SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS82032 operates on a 3.3 V power supply and all inputs/

outputs are 3.3 V- and 2.5 V-compatible. Separate output

power (V

internal circuit.

DDQ

) pins are used to decouple output noise from the

GS82032T/Q-150/138/133/117/100/66

3.3 V and 2.5 V I/O

150 MHz–66 MHz

Preliminary

9 ns–18 ns

3.3 V V

Related parts for GS82032T-5

GS82032T-5 Summary of contents

Page 1

... The GS82032 operates on a 3.3 V power supply and all inputs/ outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V internal circuit address burst 2 3 1/23 Preliminary GS82032T/Q-150/138/133/117/100/66 150 MHz–66 MHz 3.3 V and 2.5 V I/O ) pins are used to decouple output noise from the DDQ © 2000, Giga Semiconductor, Inc. 9 ns– ...

Page 2

... DDQ Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032T/Q-150/138/133/117/100/66 64K x 32 Top View 2/23 Preliminary ...

Page 3

... Flow Through or Pipeline mode; active low LBO DDQ 3/23 Preliminary GS82032T/Q-150/138/133/117/100/66 Description Address Inputs Data Input and Output pins No Connect , DQ Data I/Os; active low Data I/Os; active low C D Clock Input Signal; active high Chip Enable; active low Chip Enable ...

Page 4

... Power Down ZZ Control Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032T/Q-150/138/133/117/100/ Counter Load Register D Q Register D Q Register D Q Register D Q Register ...

Page 5

... may be used in any combination with BW to write single or multiple bytes. D 5/23 Preliminary GS82032T/Q-150/138/133/117/100/ A[1:0] A[1:0] A[1:0] A[1: Notes ...

Page 6

... None X L None Next CR X Next CR H Next CW X Next 6/23 Preliminary GS82032T/Q-150/138/133/117/100/66 ADSP ADSC ADV ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 7/23 Preliminary GS82032T/Q-150/138/133/117/100/ First Read Burst Read and Write ( BW, and GW) control ...

Page 8

... Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 8/23 Preliminary GS82032T/Q-150/138/133/117/100/ First Read Burst Read CR © 2000, Giga Semiconductor, Inc. ...

Page 9

... Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032T/Q-150/138/133/117/100/66 Value Unit –0.5 to 4.6 –0 – ...

Page 10

... Test conditions 3 OUT OUT Layer Board Symbol R single JA R four 10/23 Preliminary GS82032T/Q-150/138/133/117/100/66 20% tKC DD IL Typ. Max. Unit TQFP Max QFP Max Unit 40 TBD C/W 24 TBD C/W 9 TBD C/W © 2000, Giga Semiconductor, Inc. ...

Page 11

... V OUT –4 mA 2.375 DDQ –4 mA 3.135 DDQ 11/23 Preliminary GS82032T/Q-150/138/133/117/100/66 Output Load 2 2.5 V 225 DQ * 225 5pF Min Max – – –1 uA 300 uA –300 – – 1.7 V 2.4 V 0.4 V © ...

Page 12

... Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032T/Q-150/138/133/117/100/66 12/23 Preliminary © 2000, Giga Semiconductor, Inc. ...

Page 13

... Preliminary GS82032T/Q-150/138/133/117/100/66 -133 -117 -100 Max Min Max Min Max — 8.5 — 10 — — 4 — 4.5 — — 2 — 2 — 2 — 2 — 2 — — ...

Page 14

... ADSP and E only sampled with ADSP or ADSC tS tH Write specified byte for 14/23 Preliminary GS82032T/Q-150/138/133/117/100/66 Deselected Write 1 inactive ADSC initiated write WR3 WR3 WR3 Deselected with and all bytes for & ...

Page 15

... E 1 masks ADSP and E only sampled with ADSP or ADSC tOHZ tOE tKQX 15/23 Preliminary GS82032T/Q-150/138/133/117/100/66 1 inactive ADSC initiated read Suspend Burst RD3 tH tH Deselected with E tKQX tHZ © 2000, Giga Semiconductor, Inc. 2 ...

Page 16

... WR1 E2 and E3 only sampled with ADSP and ADSC tOHZ 16/23 Preliminary GS82032T/Q-150/138/133/117/100/66 Burst Read ADSP is blocked by E inactive E1 masks ADSP Deselected with Burst wrap around to its initial state © 2000, Giga Semiconductor, Inc. ...

Page 17

... E1 masks ADSP and E only sampled with ADSP or ADSC tH tOE tOHZ tKQX tOLZ tLZ tKQ 17/23 Preliminary GS82032T/Q-150/138/133/117/100/66 1 inactive ADSC initiated read Suspend Burst RD3 tH tH Deselected with E tKQX © 2000, Giga Semiconductor, Inc ...

Page 18

... WR1 E2 and E3 only sampled with ADSP and ADSC tOE tOHZ tS tH tKQ 18/23 Preliminary GS82032T/Q-150/138/133/117/100/66 Burst Read ADSP is blocked by E inactive ADSC initiated read E1 masks ADSP Deselected with © 2000, Giga Semiconductor, Inc ...

Page 19

... Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tKC tKH tKL tZZS tZZH Snooze 19/23 Preliminary GS82032T/Q-150/138/133/117/100/66 tZZR © 2000, Giga Semiconductor, Inc. ...

Page 20

... PD LD Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Out (Pull Down) VDDQ - V Out (Pull Up 20/23 Preliminary GS82032T/Q-150/138/133/117/100/66 VDDQ I Out VOut VSS 2.5 3 3 © 2000, Giga Semiconductor, Inc. 4 ...

Page 21

... Min. Nom. Max Standoff 0.05 0.10 0.15 1.35 1.40 1.45 Lead Width 0.20 0.30 0.40 0.09 — 0.20 21.9 22.0 22.1 19.9 20.0 20.1 15.9 16.0 16.1 13.9 14.0 14.1 Lead Pitch — 0.65 — Foot Length 0.45 0.60 0.75 Lead Length — 1.00 Coplanarity — — 0.10 Lead Angle 0 — 7 21/23 Preliminary GS82032T/Q-150/138/133/117/100/66 QFP Min. Nom. Max 0.25 0.35 0.45 2.55 2.72 2.90 0.20 0.30 0.40 0.10 0.15 0.20 22.95 23.2 23.45 19.9 20.0 20.1 17.0 17.2 17.4 13.9 14.0 14.1 — 0.65 — .60 0.80 1.00 — 1.60 — — — 0.10 0 — 7 © 2000, Giga Semiconductor, Inc. ...

Page 22

... GS82032T-5 64K x 32 GS82032T-6 64K x 32 GS82032T-150I 64K x 32 GS82032T-138I 64K x 32 GS82032T-133I 64K x 32 GS82032T-4I 64K x 32 GS82032T-5I 64K x 32 GS82032T-6I 64K x 32 GS82032Q-150 64K x 32 GS82032Q-138 64K x 32 GS82032Q-133 64K x 32 GS82032Q-4 64K x 32 GS82032Q-5 64K x 32 ...

Page 23

... New GSI Logo Format/Content • Switched TKQ with TCycle in Flow Through part of table on page 1. • Updated format to comply with Technical Publication Standards Format/Content • Changed all -4 references in ordering information table on page 22 from 117/11 to 133/10. 23/23 Preliminary GS82032T/Q-150/138/133/117/100/66 © 2000, Giga Semiconductor, Inc. ...

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