GS881Z18T-100 GSI Technology, GS881Z18T-100 Datasheet

GS881Z18T-100

Manufacturer Part Number

GS881Z18T-100

Description

100MHz 12ns 512K x 18 8Mb pupelined and flow through sync NBT SRAM

Manufacturer

GSI Technology

Datasheet

1.GS881Z18T-100.pdf (34 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• 512K x 18 and 256K x 36 configurations

• User-configurable Pipelined and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Read-Write-Read bus utilization

• Fully pin-compatible with both pipelined and flow through

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• Pin-compatible with 2M, 4M and 16M devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered, address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

Rev: 1.10 8/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Flow Through

NtRAM™, NoBL™ and ZBT™ SRAMs

Read/Write

Pipelined

Address

Data I/O

Clock

Cycle

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

210 mA

150 mA

4.5 ns

10 ns

11 ns

15 ns

8Mb Pipelined and Flow Through

-11

Synchronous NBT SRAMs

210 mA

150 mA

4.5 ns

10 ns

12 ns

15 ns

-100

190 mA

130 mA

12.5 ns

4.8 ns

14 ns

15 ns

-80

170 mA

130 mA

15 ns

18 ns

20 ns

5 ns

1/34

-66

Functional Description

The GS881Z18/36T is an 8Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS881Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising-edge-triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge-triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

The GS881Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

GS881Z18/36T-11/100/80/66

2.5 V and 3.3 V V

100 MHz–66 MHz

Preliminary

3.3 V V

DDQ

Related parts for GS881Z18T-100

GS881Z18T-100 Summary of contents

Page 1

Pipelined and Flow Through 100-Pin TQFP Commercial Temp Synchronous NBT SRAMs Industrial Temp Features • 512K x 18 and 256K x 36 configurations • User-configurable Pipelined and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero ...

Page 2

... GS881Z18T Pinout 100 DDQ DDQ DDQ ...

Page 3

GS881Z36T Pinout 100 DDQ ...

Page 4

TQFP Pin Descriptions Pin Location Symbol 37 35, 34, 33, 32, 100, 99, 83, 82 81, 50, 49, 48, 47, 46, 45 ...

Page 5

Pin Location Symbol 38 TMS 39 TDI 42 TDO 43 TCK V 15, 41, 65, 91 5,10, 17, 21, 26, 40, 55, 60, 67, V 71, 76 11, 20, 27, 54, 61, 70, 77 DDQ 16 DP ...

Page 6

GS881Z18/36 ByteSafe NBT SRAM Functional Block Diagram Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Amps Sense Drivers Write 6/34 Preliminary . GS881Z18/36T-11/100/80/66 © 1998, Giga Semiconductor, Inc. ...

Page 7

Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...

Page 8

Synchronous Truth Table Operation Type Address E Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Continue D Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R ...

Page 9

Pipeline and Flow Through Read-Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for ...

Page 10

Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.10 8/2000 Specifications cited ...

Page 11

Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.10 8/2000 Specifications cited are subject to ...

Page 12

Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...

Page 13

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I Sleep mode is dictated by the length of time the High state. After entering Sleep mode, ...

Page 14

Write Parity Error Output Timing Diagram Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com tKQ tHZ tKQX tLZ ...

Page 15

Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...

Page 16

Undershoot Measurement and Timing 50% V – 2 20% tKC Capacitance 3 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 17

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 18

Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current IH IL Output open Standby ZZ V – 0 Current Device Deselected; Deselect All other inputs Current Rev: ...

Page 19

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- through Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 20

Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...

Page 21

Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...

Page 22

Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...

Page 23

Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV W Bn – Write COMMAND D(A1) *Note High (False ...

Page 24

JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for ...

Page 25

Page 26

Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions not 1194.1- compliant because some of the mandatory ...

Page 27

Register. Because the RAM clock is independent from the TAP Clock (TCK possible for the TAP to attempt to capture the I/O ring con- tents while the input buffers are in transition (i. metastable state). Although ...

Page 28

JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output ...

Page 29

JTAG Port Timing Diagram tTKH tTKL TCK TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI ...

Page 30

GS881Z18/36T TQFP Boundary Scan Register Order x36 x18 Pin n n ...

Page 31

Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For ...

Page 32

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 33

... GS881Z18T-80 512K x 18 GS881Z18T-66 256K x 36 GS881Z36T-11 256K x 36 GS881Z36T-100 256K x 36 GS881Z36T-80 256K x 36 GS881Z36T-66 512K x 18 GS881Z18T-11I 512K x 18 GS881Z18T-100I 512K x 18 GS881Z18T-80I 512K x 18 GS881Z18T-66I 256K x 36 GS881Z36T-11I 256K x 36 GS881Z36T-100I 256K x 36 GS881Z36T-80I 256K x 36 GS881Z36T-66I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “ ...

Page 34

Types of Changes DS/DateRev. Code: Old; Format or Content New GS881Z18/36TRev1.04h 5/ 1999; 1.05 9/1999 GS881Z18/36T 1.05 9/ 1999K/ 1.06 10/1999 GS881Z18/36T 1.06 9/ 1999K 1.07 1/2000L Rev.1.08; 881Z18_r1_09 881Z18_r1_09; 881Z18_r1_10 Rev: 1.10 8/2000 Specifications cited are subject to change ...

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