VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 99/128:

General Purpose Power Management Registers

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF

General Purpose Power Management Registers

I/O Offset 21-20 - General Purpose Status (GP_STS) . RWC
........................................ always reads 0
15
Reserved
14
USB Wake-Up Status (UWAK_STS)
For STR / STD / Soff
13
AC97 Wake-Up Status (AWAK_STS)
Can be set only in suspend mode
12
Battery Low Status (BL_STS)
This bit is set when the BATLOW# input is asserted
low.
11
Notebook Lid Status (LID_STS)
This bit is set when the LID input detects the edge
selected by Rx2C bit-7 (0=rising, 1=falling).
10
Thermal Detect Status (THRM_STS)
This bit is set when the THRM input detects the edge
selected by Rx2C bit-6 (0=rising, 1=falling).
9
USB Resume Status (USB_STS)
This bit is set when a USB peripheral generates a
resume event.
8
Ring Status (RING_STS)
This bit is set when the RING# input is asserted low.
7
GPI18 Toggle Status (GPI18_STS)
This bit is set when the GPI18 pin is toggled.
6
GPI6 / EXTSMI6 Toggle Status (GPI6_STS)
This bit is set when the GPI6 pin is toggled.
5
GPI5 Toggle Status (GPI5_STS)
This bit is set when the GPI5 pin is toggled.
4
GPI4 / EXTSMI4 Toggle Status (GPI4_STS)
This bit is set when the GPI4 pin is toggled.
3
GPI17 Toggle Status (GPI17_STS)
This bit is set when the GPI17 pin is toggled.
2
GPI16 Toggle Status (GPI16_STS)
This bit is set when the GPI16 pin is toggled.
1
GPI1 Toggle Status (GPI1_STS)
This bit is set when the GPI1 pin is toggled.
0
EXTSMI# Status (EXT_STS)
This bit is set when the EXTSMI# pin is asserted low.
Note that the above bits correspond one for one with the bits
of the General Purpose SCI Enable and General Purpose SMI
Enable registers at offsets 22 and 24: an SCI or SMI is
generated if the corresponding bit of the General Purpose SCI
or SMI Enable registers, respectively, is set to one.
The above bits are set by hardware only and can only be
cleared by writing a one to the desired bit.
Revision 1.71 June 9, 2000
I/O Offset 23-22 - General Purpose SCI Enable ............ RW
........................................always reads 0
15
Reserved
14
Enable SCI on setting of the UWAK_STS bit def=0
Enable SCI on setting of the AWAK_STS bit def=0
13
12
Enable SCI on setting of the BL_STS bit ......def=0
Enable SCI on setting of the LID_STS bit .....def=0
11
10
Enable SCI on setting of the THRM_STS bit def=0
Enable SCI on setting of the USB_STS bit ....def=0
9
8
Enable SCI on setting of the RING_STS bit .def=0
7
Enable SCI on setting of the GPI18_STS bit..def=0
6
Enable SCI on setting of the GPI6_STS bit....def=0
5
Enable SCI on setting of the GPI5_STS bit....def=0
4
Enable SCI on setting of the GPI4_STS bit....def=0
3
Enable SCI on setting of the GPI17_STS bit..def=0
2
Enable SCI on setting of the GPI16_STS bit..def=0
1
Enable SCI on setting of the GPI1_STS bit....def=0
0
Enable SCI on setting of the EXT_STS bit ....def=0
These bits allow generation of an SCI using a separate set of
conditions from those used for generating an SMI.
I/O Offset 25-24 - General Purpose SMI Enable ........... RW
15-14 Reserved
........................................always reads 0
13
Enable SMI on setting of the AWAK_STS bit def=0
12
Enable SMI on setting of the BL_STS bit .....def=0
11
Enable SMI on setting of the LID_STS bit ....def=0
10
Enable SMI on setting of the THRM_STS bit def=0
9
Enable SMI on setting of the USB_STS bit ...def=0
8
Enable SMI on setting of the RING_STS bit def=0
7
Enable SMI on setting of the GPI18_STS bit.def=0
6
Enable SMI on setting of the GPI6_STS bit...def=0
5
Enable SMI on setting of the GPI5_STS bit...def=0
4
Enable SMI on setting of the GPI4_STS bit...def=0
3
Enable SMI on setting of the GPI17_STS bit.def=0
2
Enable SMI on setting of the GPI16_STS bit.def=0
1
Enable SMI on setting of the GPI1_STS bit...def=0
0
Enable SMI on setting of the EXT_STS bit....def=0
These bits allow generation of an SMI using a separate set of
conditions from those used for generating an SCI.
-93-
Power Management I/O-Space Registers
VT82C686B