AK8851VQ AKM Semiconductor, Inc., AK8851VQ Datasheet
AK8851VQ
Available stocks
Related parts for AK8851VQ
AK8851VQ Summary of contents
Page 1
ASAHI KASEI NTSC/PAL/SECAM Digital Video Decoder The AK8851 is an integrated chip that decodes NTSC, PAL, SECAM composite and S Video signals.. The digital output of the AK8851 is ...
Page 2
ASAHI KASEI 1.Functional Block Diagram CLK CLOCK IRefR1 Module EXTCLP Analog Process AIN1 AIN2 - Analog Multiplexer CVBS AIN3 - Clamp - PGA Y AIN4 AIN5 C AIN6 CLPCA P1 CLPCA P2 VREF VRP VCOM VRN AVDD AVSS MS0244-E-03 SELA ...
Page 3
ASAHI KASEI 2. Pin Assignment DVSS 76 CLKINV 77 /RESET 78 /PD 79 EXTCLP 80 ...
Page 4
ASAHI KASEI 3. Pin Functional Description PIN# Symbol I/O 1 VRP O Internal reference positive Voltage for AD Converter 2 VRN O Internal reference negative Voltage for AD Converter 3 VCOM O Common voltage for AD Converter 4 AVSS G ...
Page 5
ASAHI KASEI 56 DVSS G Ground pin for Digital 57 DVDD P Digital supply voltage (3.3V) Indicator for Y Data and Cb/Cr Data in 8-bit output mode 58 HALFCKO O (Indicator transition rate is 13.5MHz) 59 CLK27MO O 27MHz Clock ...
Page 6
ASAHI KASEI 4.Electrical Specifications (1) Absolute Maximum Ratings Parameter Supply Voltage* (VDD) DVDD, AVDD Input Pin Voltage (Vin) Input Pin Current (Iin) Storage Temperature Note) power supply voltages are referenced to each ground pin (DVSS, AVSS) which is equal to ...
Page 7
ASAHI KASEI (5) Analog Characteristics and Power Dissipation (AVDD =3 room temperature) Selector Clamp Parameter Symbol Maximum Input Range VIMX Clamp Level VYCP (Composite / Y Video Signal) C Signal Clamp Level VCCP Clamp Current CLPI Isolation between ...
Page 8
ASAHI KASEI 5. AC Timing ( DVDD=3 deg (1) Clock Input Parameter Symbol CLK fSYSCLK CLK Pulse width H tCLKH CLK Pulse width L tCLKL Frequency stability (2)CLK27MO output ...
Page 9
ASAHI KASEI (3) Output Data Timing (3-1) Output Data Timing (except for D[7:0] and EXTDAT[7:0] in 16-Bit output mode and NSIG output) CLKINV=Low CLK27MO tODL1 tOHD1 Output Data CLKINV=High CLK27MO tODL1 tOHD1 Output Data Parameter Symbol Output Data Delay Time ...
Page 10
ASAHI KASEI (3-2) 16-Bit Output Data Timing ([D7:D0] and [EXTDAT7:EXTDAT0]) HALFCKO [D7:0] EXTDAT7:0] Parameter Symbol Output Data Setup Time tOSU3 Output Data Hold Time tOHD3 (4) Reset Timing / RESET CLK Parameter Symbol /RESET Pulse width pRES Note) a 24.576 ...
Page 11
ASAHI KASEI (5) /PD pin release reset Before setting /PD pin to Low, at least 100 clock cycles must be applied to the device.. After releasing /PD pin to high, the /RESET pin must be kept low until the analog ...
Page 12
ASAHI KASEI (7) I2C bus Input and Output Timing (7-1) Timing 1 : tHD STA tBUF SDA tF SCL Item Bus Free Time Hold Time (Start Condition) Clock Pulse Low Time Input Signal Rise Time Input Signal Fall Time Setup ...
Page 13
ASAHI KASEI 6. Functional Summary (1) Clock The AK8851 operates in one of 3 clock modes. 1. Line Locked Clock mode: An operating mode where the device uses a clock that is synchronized with the Horizontal Sync signal for each ...
Page 14
ASAHI KASEI (8) Y/C Separation Function For NTSC,NTSC-4.43 signal inputs : Adaptive Y/C separation is used also possible to lock this function to either 3-line 2 dimensional Y/C separation, or primary dimensional (BPF) Y/C separation. For PAL-B,D,G,H,I,M,N,Nc,NTSC-4.43,PAL 60 ...
Page 15
ASAHI KASEI 7. Input Signal Selector The AK8851 has 4 analog signal input pins. Signal selection is done by [AFE Control Register](R/W)[Sub Address 0x00] and the type of Video signals to be decoded is set by [Input Video Standard Register](R/W)[Sub ...
Page 16
ASAHI KASEI [Input Video Standard Register](R/W)[Sub Address 0x01]: This register sets the input signal attributes. its Bit Allocation is as follows. Sub Address 0x01 bit 7 bit 6 bit 5 AUTODET SETUP B [VSCF1:VSCF0]-bit: Input signal ...
Page 17
ASAHI KASEI [AUTODET]-bit: SET the [AUTODET]-bit in order to automatically distinguish input signals. [AUTODET]-bit 0 1 (footnote) following input signal characteristics are automatically detected. Number of Lines per each Frame:525/625 Sub-Carrier frequency : 3.58/4.43 MHZ Color Encoding systems: NTSC/PAL/SECAM With ...
Page 18
ASAHI KASEI *[ST-B/W]-bit: when the input signal is Black and White,[ST-B/W]-bit indicates the status. [ST_B/W]-bit 0 1 Since Black and White signal decisions are made by the color killer level, the color killer bit must be turned “ON”. When a ...
Page 19
ASAHI KASEI 8.PGA ( Programmable Gain Amp.) The Ak8851 has 2 PGAs (Programmable Gain Amps), PGA1 and PGA2 on the input stage. The gain range of each PGA is from 0dB to 12dB with a gain step of approx. 0.1 ...
Page 20
ASAHI KASEI [AGCT1:AGCT0]-bit: * AGC time constant is set by [AGCT1:AGCT0]-bit. [AGCT1:AGCT0]-bit [00] [01] [10] [11] [AGCC]-bit: *[AGCC]-bit sets the non-sensing range ( coring level ) of AGC. [AGCC]-bit 0 1 [AGCFRZ]-bit: * This bit controls the AGC freeze function. ...
Page 21
ASAHI KASEI 10.CLAMP [Analog Clamp circuit]: The AK8851 uses an analog circuit to clamp the input signal to the Sync-Tip level (Analog Sync-Tip clamp). Clamp timing is set by [AFE Control Register](R/W)[Sub Address 0x00]. The clamp timing pulse is generated ...
Page 22
ASAHI KASEI [CLPSTAT1:CLPSTAT0]-bit: This sets the clamp position of input signal. The clamp timing pulse position is internally generated by the AK8851. Clamp timing pulse is generated at the center position of SYNC signal. Its pulse position is adjustable(refer to ...
Page 23
ASAHI KASEI 11. CLOCK The AK8851 operates under the following ,3 clock modes. (1) Line-Locked Clock Mode A clock can be derived from the Horizontal SYNC signal (HSYNC input signal. This input signal can be a high quality ...
Page 24
ASAHI KASEI 12. Decimation Filter In the AK8851, the input signal is 2x over-sampled at 27 MHz, which is synchronized with the input signal, then it is down-sampled to 13.5 MHz using a decimation filter. The decimation filter’s frequency response ...
Page 25
ASAHI KASEI 14. Digital Pedestal Clamp The input signal’s digitally-converted Pedestal position is clamped in the digital signal-processing block. It handles 2 types of input signals (286 mV-type SYNC signal and 300 mV-type SYNC signal) and it outputs the pedestal ...
Page 26
ASAHI KASEI 16. Auto Color Control ( ACC ) This function adjusts the input signal’s Color Burst level to its appropriate level (NTSC:286 [mV]/ PAL:300 [mV]). The ACC control value can be frozen by register settings. The input color signal ...
Page 27
ASAHI KASEI [CKSCM1:CKSCM0]-bit: This sets the level to activate the Color Killer function in SECAM mode. 18. Black and White Mode Black and White mode is to process all input signals as Y signal. In this mode, C signal output ...
Page 28
ASAHI KASEI 20.Image Quality Adjusting Function The AK8851 has Image Quality Adjusting functions that include Contrast, Brightness, Sharpness , Color Saturation and Hue adjustments. By default, the Image Quality adjustment function is invalid during the Vertical Blanking period. However Contrast ...
Page 29
ASAHI KASEI (3) Sharpness Control For sharpness control, the following signal processing is performed on the Luminance (Y) signal as shown in the block diagram below. One of the 3 different type filter characteristics in the block is selected by ...
Page 30
ASAHI KASEI (4) Color Saturation Control Color Saturation adjustment is made by multiplying the Chroma signal (C) with a fixed value set by [Saturation Control Register](R/W)[Sub Address 0x11]. The Saturation factor is performed on C signal. A result of multiplied ...
Page 31
ASAHI KASEI (7) Luminance Bandwidth Adjustment To maximize the compression ratios in MPEG and other digital video formats often desirable to limit the Luminance bandwidth through pre-processing before compression. T. For this purpose, Luminance signal band-limiting-filters can be ...
Page 32
ASAHI KASEI 21. Vertical Blanking Interval Setting of Vertical Blanking Interval and selecting tasks to be performed during this interval are set by [Output Format Register](R/W)[Sub Address 0x02]. Default values of Vertical Blanking Interval are as follows: 525 Line system ...
Page 33
ASAHI KASEI < V-bit value vs. Line relation > NTSC(525 System) TRSVSEL=0 ITU-R Bt.656-3 V-bit Line10~Line263 V-bit = 0 Line273~Line525 Line1~Line9 V-bit = 1 Line264~Line272 note) TRSVSEL-bit setting applies to all 525 and 625 Line systems as shown in the ...
Page 34
ASAHI KASEI (1) VBIDEC[1:0]-bit = 00 (525-Line) 524 525 Normal Decode operation 263 264 265 266 (2) VBIDEC[1:0]-bit = 01 (525-Line) 524 525 Normal Decode Operation 263 264 265 266 (2) VBIDEC[1:0]-bit = 10 ...
Page 35
ASAHI KASEI (1) VBIDEC[1:0]-bit = 00 (625-Line) 622 623 624 625 Normal Decode Operation 310 311 312 313 (2) VBIDEC[1:0]-bit = 01 (625-Line) 622 623 624 625 Normal Decode Operation 310 311 312 313 (2) VBIDEC[1:0]-bit = 10 (625-Line) 622 ...
Page 36
ASAHI KASEI 22. Closed Caption/Closed Caption Extended Data/ VBID ( CGMS )/WSS The AK8851 decodes Closed Caption, Closed Caption extended, , VBID (CGMS) and WSS signals that are super-imposed on the Vertical Blanking signal. Decoded data is written into a ...
Page 37
ASAHI KASEI Read Operation of Closed Caption Data: When the CCRQ-bit is “1”, the AK8851 is placed into a wait state for the Closed Caption data decoding. Data is decoded as data is received, and after the decoding is completed, ...
Page 38
ASAHI KASEI Read Operation of WSS Data : When the WSSRQ-bit = “1”, the AK8851 is put into a wait state for the WSS data decoding. Data is decoded as data is received, and after the decoding is completed, ”1” ...
Page 39
ASAHI KASEI 23. VBI Slice Function The AK8851 has a function to slice VBI data. The sliced data is output in 601 digital format. The VBI slice function is handled in the Luminance signal-processing path. In the VBI function, the ...
Page 40
ASAHI KASEI [SLLVL1 : SLLVL0]-bit : * Those are to set the slice level. [SLLVL]-bit 0 1 High and low values of the sliced and binary-converted data are set by [High Data Set Register] and [Low Data Set Register].The values ...
Page 41
ASAHI KASEI 24. MACROVISION Decoder When a MACROVISION copy-protected signal is fed to the input, the AK8851 decodes the added MACROVISION information and stores its result in [Macrovision Status Register](R)[Sub Address 0x18]. Configuration of [Macrovision Status Register] is shown below. ...
Page 42
ASAHI KASEI 25. Decode Data Output ( Rec.601 limit / YC Delay / Timing ) The AK8851 outputs decoded data in ITU-R BT.601 compatible format (Y /Cb /Cr 4:2:2). The minimum and maximum output code values are selectable by the ...
Page 43
ASAHI KASEI [ACTSTAT2 : ACTSTAT0]-bit : This bit allows fine-tuning of the Active Video Start Position. The Default Start Position is shown in the following diagram (information from Rec.601 specification 122nd Sample (525-System) [ACTSTAT2:ACTSTAT0]-bit 525-System: Active Video starts ...
Page 44
ASAHI KASEI 26. Output Interface (1) ITU-R BT.656 Interface The AK8851 outputs decoded data in ITU-R BT.656 compatible interface format. ITU-R BT.656 compatible output data means: * Samples per Line: 858 samples (525 system)/864 samples (625 system) * Line numbers ...
Page 45
ASAHI KASEI (2) Interface by DVALID Signal When the ITU-R BT.656 interface is not available, the AK8851 can output data by the DVALID signal that becomes valid during the Active Video interval. DVALID signal and data output relation is shown ...
Page 46
ASAHI KASEI (4) Output of Various Timing Signals The AK8851 generates following timing signal outputs. Pin Name 15.734kHz Interval. Low interval is about HSYNC 4.7[usec] Low output between VSYNC Line4 ~ Line6 / Line266.5~Line269.5 CSYNC FIELD DVALID * Output Timing ...
Page 47
ASAHI KASEI 27.Blue-Back Function The Output can be set to Blue-Back mode by setting a register via the host CPU. The output code at Blue-Back mode is Y=41,Cb=240,Cr=110 The Blue-Back mode set is done by [BLUEBACK]-bit of [Control 2 Register]((R/W)[Sub ...
Page 48
ASAHI KASEI 30. Status Information Function of Internal Operation The AK8851 has [Status 1 Register] to show the internal status. Bit Allocation of [Status 1 Register follows. Sub Address 0x16 bit 7 bit 6 bit 5 OVCOL PKWHITE ...
Page 49
ASAHI KASEI (5) Overflow Indication of Input Signal Level The AK8851 has 2 types of overflow indicators,” Luminance signal overflow indication “ and “ Chroma signal overflow indication “ to indicate that the ADC input signal has exceeded its acceptable ...
Page 50
ASAHI KASEI 31. Power Down Mode The AK8851 has a Power-Saving mode. To put only the Analog functional blocks into this mode, set the input set bits [INSEL1:INSEL0]-bit to [1,1,1] of [AFE Control Register](R/W)[Sub Address 0x00]. In this case, Analog ...
Page 51
ASAHI KASEI 32. Device Control Interface The AK8851 operation is controlled via I2C bus control interface. [I2C Bus SLAVE Address] Either of 0x88 or 0x8A I2C Slave Address is selected by SELA pin. SELA SLAVE Address PULL DOWN [LOW] 0x88 ...
Page 52
ASAHI KASEI 33.Register Definition Sub Register Address 0x00 AFE Control Register 0x01 Input Video Select Register 0x02 Output Format Register 0x03 Reserved Register 0x04 Out Control Register 0x05 Start and Delay Control Register 0x06 AGC and ACC Control Register 0x07 ...
Page 53
ASAHI KASEI AFE Control Register (R/W) [Sub Address 0x00] This sets the Analog Front End functions. Input signal selection and analog clamp control related-tasks are set. Generation Clamp pulse timing and its pulse width can be adjusted to control the ...
Page 54
ASAHI KASEI Input Video Standard Register (R/W) [Sub Address 0x01] Register to set various input signal characteristics Sub Address 0x01 bit 7 bit 6 bit 5 AUTODET SETUP B Input Video Standard Register Definition BIT Register Name ...
Page 55
ASAHI KASEI Output Format Register (R/W) [Sub Address 0x02] Register to set the format of output data. The following contents are pre-settable * Vertical Blanking Interval * Upper / Lower limits of 601 data * handling of output if ITU-R ...
Page 56
ASAHI KASEI Reserved Register (R/W) [Sub Address 0x03] Reserved Register Sub Address 0x03 bit 7 bit 6 bit 5 Reserved Reserved Reserved MS0244-E-03 bit 4 bit 3 bit 2 Reserved Reserved Reserved Default Value ...
Page 57
ASAHI KASEI Out Control Register (R/W) [Sub Address 0x04] Register to fix the output pin status. Sub Address 0x04 bit 7 bit 6 bit 5 Reserved Reserved Reserved Start and Delay Control Register Definition BIT Register Name ...
Page 58
ASAHI KASEI Start and Delay Control Register (R/W) [Sub Address 0x05] Register to set the output data Sub Address 0x05 bit 7 bit 6 bit 5 Reserved ACTSTAT2 ACTSTAT1 Start and Delay Control Register Definition BIT Register ...
Page 59
ASAHI KASEI AGC and ACC Control Register (R/W) [Sub Address 0x06] Register to set the AGC and ACC characteristics. Sub Address 0x06 bit 7 bit 6 bit 5 ACCFRZ ACC1 ACC0 AGC and ACC Control Register Definition ...
Page 60
ASAHI KASEI Reserved Register (R/W) [Sub Address 0x07] Reserved Sub Address 0x07 bit 7 bit 6 bit 5 Reserved Reserved Reserved MS0244-E-03 bit 4 bit 3 bit 2 Reserved Reserved Reserved Default Value ...
Page 61
ASAHI KASEI Control 1 Register (R/W) [Sub Address 0x08] Control register to set various functions as shown in the table below. Sub Address 0x08 bit 7 bit 6 bit 5 CLKMODE1 CLKMODE0 INTPOL1 Control 1 Register Definition ...
Page 62
ASAHI KASEI Control 2 Register (R/W) [Sub Address 0x09] Control register to set various functions as shown in the table below. Sub Address 0x09 bit 7 bit 6 bit 5 Reserved ERRHND1 STUPATOFF Control 2 Register Definitions ...
Page 63
ASAHI KASEI PGA1 Control Register (R/W) [Sub Address 0x0A] Set PGA1 Sub Address 0x0A bit 7 bit 6 bit 5 Reserved PGA1_6 PGA1_5 PGA1 Control Register Definition BIT Register Name bit 0 PGA1_0 ~ ~ PGA1 Gain ...
Page 64
ASAHI KASEI Pedestal Level Control Register (R/W) [Sub Address 0x0C] Fine adjustment of Pedestal Level Sub Address 0x0C bit 7 bit 6 bit 5 DPCC1 DPCC0 DPCT1 Black Level Adjust Register Definition BIT Register Name bit 0 ...
Page 65
ASAHI KASEI Color Killer Control Register (R/W) [Sub Address 0x0D] Setting the color killer function Sub Address 0x0D bit 7 bit 6 bit 5 COLKILL Reserved CKSCM1 Color Killer Control Register Definition BIT Register Name bit 0 ...
Page 66
ASAHI KASEI Contrast Control Register (R/W) [Sub Address 0x0E] Register to set Contrast adjustment. Default value ( 0x80 ) corresponds to un-adjusted condition. Sub Address 0x0E bit 7 bit 6 bit 5 CONT7 CONT6 CONT5 Contrast Control ...
Page 67
ASAHI KASEI Image Control Register (R/W) [Sub Address 0x10] Register to control sharpness of image. For sharpness and softness filter characteristics and Luminance band-limiting filter characteristics, please refer to the corresponding sections of this data sheet. Sub Address 0x10 bit ...
Page 68
ASAHI KASEI Saturation Control Register (R/W) [Sub Address 0x11] This adjusts the color saturation level. The default value of 0x80 corresponds to the un-adjusted value. Sub Address 0x11 bit 7 bit 6 bit 5 SAT7 SAT6 SAT5 ...
Page 69
ASAHI KASEI High Data Set Register (R/W) [Sub Address 0x13] Register to set “HIGH” level of binary-coded data that is sliced by the VBI Slicer. The default value is equal to 100 % White level ( 235 ). Sub Address ...
Page 70
ASAHI KASEI Request VBI Info Register (R/W) [Sub Address 0x15] This Register requests VBLANK decode information such as Closed Caption data/Extended data/ VBID (CGMS)/WSS data. When “1” is written into each decode request bit of VBLANK information register, the AK8851 ...
Page 71
ASAHI KASEI Status 1 Register (R/W) [Sub Address 0x16] Status 1 Register (R/W)[ Sub Address 0x16] This is to show the internal state of the AK8851. Sub Address 0x16 bit 7 bit 6 bit 5 OVCOL PKWHITE SCLKMODE1 Status 1 ...
Page 72
ASAHI KASEI Status 2 Register (R/W) [Sub Address 0x17] This is to show the internal state of the AK8851 Sub Address 0x17 bit 7 bit 6 bit 5 Reserved Reserved Reserved Status2 Register Definition BIT Register Name bit 0 CCDET ...
Page 73
ASAHI KASEI Macrovision Status Register (R/W) [Sub Address 0x18] This register detects Macrovision data. Sub Address 0x18 bit 7 bit 6 bit 5 Reserved Reserved Reserved Macrovision Status Register Definition BIT Register Name bit 0 AGCDET AGC Process Detect bit ...
Page 74
ASAHI KASEI Input Video Status Register (R) [Sub Address 0x19] This shows a result of automatic input signal distinguishing function. Sub Address 0x19 bit 7 bit 6 bit 5 Fixed Undef ST_B/W Input Video Status Register Definition BIT Register Name ...
Page 75
ASAHI KASEI Closed Caption 1 Register (R) [Sub Address 0x1A] Register to store the Closed Caption data. Sub Address 0x1A bit 7 bit 6 bit 5 CC7 CC6 CC5 Closed Caption 2 Register (R) [Sub Address 0x1B] Register to store ...
Page 76
ASAHI KASEI Device and Revision ID Register (R) [Sub Address 0x22] Register to indicate the device ID and revision number of the AK8851. The device ID of the AK8851 decimal format. Revision number is renewed only when ...
Page 77
ASAHI KASEI 34. System connection Micro Processor (I2C Controller) Video IN Anti-arias 39: Filter 39: 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 24.576MHz Clock X’tal 24.576 Analog 3.3V MS0244-E-03 SDA SCL /RESET /PD 0.1u AIN1..6 CLPCAP1 CLPCAP2 IRefR2 VRP VCOM VRN ...
Page 78
ASAHI KASEI 35 Package 16 100 1 0.5 0.10 MS0244-E-03 14 0.22 r 0.05 0.10 M 1.0 0.5 r 0.2 78 Confidential [AK8851] 1.70 Max 1.40 0.20 Max 0.17 r 0.05 0 ...
Page 79
... ASAHI KASEI 36 Marking 1 1) AKM : AKM Logo 2) AK8851VQ : Marketing Code 3) XXXXXXX (7digits) : Date Code Pin #1 indication MS0244-E-03 AK8851VQ 79 Confidential [AK8851] 2005 / 07 ...
Page 80
ASAHI KASEI x These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. x AKM assumes ...