AK4537VN AKM Semiconductor, Inc., AK4537VN Datasheet
AK4537VN
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AK4537VN Summary of contents
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ASAHI KASEI 16-Bit The AK4537 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The ...
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ASAHI KASEI 10. Audio Interface Format : MSB First, 2’s compliment 2 ADC : I S, 16bit MSB justified 2 DAC : I S, 16bit MSB justified, 16bit LSB justified 11 - 12. Power Supply: 13. ...
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... MICOUTR 2 EXT/MICR 3 MPE 4 MPI 5 INT/MICL 6 VCOM 7 AVSS 8 AVDD 9 PVDD 10 PVSS 11 VCOC MS0202-E-04 +70 C 52pin QFN (0.4mm pitch AK4537VN Top View [AK4537 MUTET 38 HPL 37 HPR 36 HVSS 35 HVDD SPN 34 33 SPP 32 ...
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ASAHI KASEI „ Comparison with AK4534 1. Function Function Line Input Mic Input IPGA Stereo Line Output SPK-Amp Gain Select MOUT Gain Select Path from IPGA Lch to Analog Output 2. Pin pin ...
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ASAHI KASEI No. Pin Name I/O 1 MICOUTL O MIC-Amp Lch Output Pin 2 MICOUTR O MIC-Amp Rch Output Pin EXT I External Microphone Input Pin (Mono Input) 3 MICR I Stereo Microphone Rch Input Pin 4 MPE O MIC ...
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ASAHI KASEI No. Pin Name I/O No Connect This pin should be left floating. 28 DVDD - Digital Power Supply Pin 29 DVSS - Digital Ground Pin 30 XTO O X’tal Output Pin XTI I X’tal Input ...
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ASAHI KASEI (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Power Supplies: Analog Digital PLL Headphone-Amp / Speaker-Amp |AVSS – PVSS| |AVSS – DVSS| |AVSS – HVSS| Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature ...
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ASAHI KASEI (Ta=25 C; AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Parameter MIC Amplifier: Input Resistance Gain (MGAIN bit = “0”) (MGAIN bit = “1”) MIC Power Supply: Output Voltage ...
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ASAHI KASEI Parameter Mono Line Output Characteristics: R Output Voltage (Note 10) MOGN=1, -17dB MOGN=0, +6dB S/(N+D) (-3dBFS) MOGN=1, -17dB MOGN=0, +6dB S/N (A-weighted) MOGN=1, -17dB MOGN=0, +6dB Load Resistance MOGN=1, -17dB MOGN=0, +6dB Load Capacitance Headphone-Amp Characteristics: R Output ...
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ASAHI KASEI Parameter BEEP Input: BEEPL, BEEPR, BEEPM pin Maximum Input Voltage (Note 13) Feedback Resistance Mono Input: MIN pin Maximum Input Voltage (Note 14) Input Resistance (Note 15) Mono Output: R =10k , DAC MIX L Output Voltage (Note ...
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ASAHI KASEI (Ta AVDD, DVDD, PVDD, HVDD=2.4 Parameter ADC Digital Filter (Decimation LPF): Passband (Note 22) 0.1dB 1.0dB 3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 23) Group Delay Distortion ADC Digital Filter (HPF): Frequency Response ...
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ASAHI KASEI (Ta AVDD, DVDD, PVDD, HVDD=2.4 Parameter High-Level Input Voltage Low-Level Input Voltage Input Voltage at AC Coupling High-Level Output Voltage Low-Level Output Voltage (Except SDA pin: Iout=200 A) (SDA pin: Iout=3mA) Input Leakage Current Note ...
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ASAHI KASEI Parameter Control Interface Timing (4-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “p” to CCLK “n” CCLK “n” to CSN “n” CDTO Delay CSN ...
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ASAHI KASEI „ Timing Diagram MCLK tCLKH LRCK BICK tBCKH MCKO dMCK 1000pF MCKI Input MS0202-E-04 1/fCLK tCLKL 1/fs tBCK tBCKL fMCK dMCK Figure 3. Clock Timing Measurement Point 100k AGND AGND Figure 4. MCKI AC Coupling Timing - 14 ...
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ASAHI KASEI LRCK tBLR BICK tLRS SDTO SDTI Figure 5. Audio Interface Timing (Slave mode) LRCK tMBLR BICK SDTO SDTI Figure 6. Audio Interface Timing (Master mode) MS0202-E-04 tLRB tBSD tSDS tSDH dBCK tBSD tSDS tSDH - 15 - [AK4537] ...
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ASAHI KASEI CSN CCLK CDTI CDTO Figure 7. WRITE/READ Command Input Timing CSN CCLK CDTI D2 CDTO MS0202-E-04 tCSS tCCKL tCCKH tCDS tCDH C1 C0 Hi-Z tCSH D1 D0 Hi-Z Figure 8. WRITE Data Input Timing - 16 - [AK4537] ...
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ASAHI KASEI CSN CCLK CDTI A1 Hi-Z CDTO CSN CCLK ...
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ASAHI KASEI SDA tBUF tLOW tR SCL tHD:STA Stop Start CSN SDTO PDN MS0202-E-04 tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 11 Bus Mode Timing tPDV tPD Figure 12. Power Down & Reset Timing - 18 - ...
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ASAHI KASEI „ Master Clock Source The AK4537 requires a master clock (MCLK). This master clock is input to the AK4537 by connecting a X’tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the ...
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ASAHI KASEI (2) External Clock Direct Input XTI External Clock XTO Figure 14. External Clock mode (Input : CMOS Level) Note: This clock level must not exceed DVDD level. (3) AC Coupling Input C XTI External Clock XTO Figure 15. ...
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ASAHI KASEI „ System Clock (1) PLL Mode (PMPLL bit = “1”) A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see Table.2 and Table.3). The frequency of the ...
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ASAHI KASEI Power up Frequency set by PLL1-0 MCKI pin bits (Refer to Table 2) MCKO bit = “0” : “L” MCKO pin MCKO bit = “1” : Output BF bit = “0” : 64fs Output BICK pin BF bit ...
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ASAHI KASEI Mode Table 8. MCKO Frequency (EXT Mode, MCKO bit = “1”) MCKO pin BICK pin LRCK pin Table 9. Clock Operation at Master Mode (EXT Mode) Power up MCKO bit = “0” : “L” ...
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ASAHI KASEI „ System Reset Upon power-up, reset the AK4537 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADL or ...
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ASAHI KASEI LRCK ...
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ASAHI KASEI „ MIC Gain Amplifier AK4537 has a Gain Amplifier for Microphone input. This gain is 0dB or 20dB, selected by the MGAIN bit (Table 14). The typical input impedance is 30k . The mic gain amp of the ...
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ASAHI KASEI „ Manual Mode The AK4537 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH ...
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ASAHI KASEI [3] Example of ALC1 Operation Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Register Name Comment LMTH Limiter detection Level LTM1-0 Limiter operation period at ZELM = ...
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ASAHI KASEI „ De-emphasis Filter The AK4537 includes the digital de-emphasis filter (tc = 50/ IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 16). DEM1 „ Bass Boost Function The BST1-0 ...
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ASAHI KASEI „ Digital Attenuator The AK4537 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R7-0 bits. When the DATTC bit = “1”, the ATTL7-0 bits control ...
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ASAHI KASEI „ BEEP Input When the PMBPS bit is set to “1”, the stereo beep input is powered up. And when the BPSHP bit is set to “1”, the input signals from the BEEPL and BEEPR pins are mixed ...
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ASAHI KASEI „ Headphone Output Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The Headphone output load resistance is min.20 . When the PMHPL and PMHPR bits are “0”, the ...
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ASAHI KASEI The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 19 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R Output powers are shown at ...
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ASAHI KASEI „ Speaker Output The output signal from analog volume is converted into a mono signal [(L+R)/2] and this signal is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono BTL output. When DAC output ...
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ASAHI KASEI 2) Using BEEPL and BEEPR pins AK4537 MOUT2 0.068u 20k 20k Figure 30. Connection example for 400mW output using BEEPL and BEEPR pins (SPKG bit = “1”) Note) 1. MOUT2 output is recommended coupled to ...
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ASAHI KASEI „ Stereo Line Output (LOUT/ROUT pins) MIC In 0dB/+20dB ATT+DAC When DAHS bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When MICL bit is “1”, Lch signal of IPGA is ...
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ASAHI KASEI „ ALC2 Operation (ALC2 bit = “1”) Input resistance of the ALC2 is 24k (typ) and centered around VCOM voltage, and the input signal level is –3.1dBV. (see Figure 33 and Figure 34. 0dBV=1Vrms=2.828Vpp) The limiter detection level ...
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ASAHI KASEI -3.3dBV FS -8dB FS-12dB -15.3dBV -8dB DATT DAC Figure 34. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT= 8.0dB, SPKG bit= “1”, ALC2= “1”) MS0202-E-04 FS-2.1dB = -5.2dBV +8.2dB -3.3dBV +8.2dB -1.9dB +2.2dB +2.2dB +4.1dB -11.3dBV +8.1dB -15.3dBV FS-4.1dB = ...
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ASAHI KASEI „ Serial Control Interface (1) 4-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on this interface consists of a ...
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ASAHI KASEI 2 (2) I C-bus Control Mode (I2C pin = “H”) The AK4537 supports the standard-mode I system (max: 400kHz). (2)-1. WRITE Operations Figure 36 shows the data transfer sequence for the I HIGH to LOW transition on the ...
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ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4537. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle ...
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ASAHI KASEI SDA SCL S start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0202-E-04 Figure 42. START and STOP Conditions Figure 43. Acknowledge on the I C-Bus ...
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ASAHI KASEI „ Register Map Addr Register Name D7 00H Power Management 1 PMVCM 01H Power Management 2 MCKPD 02H Signal Select1 MOGN 03H Signal Select2 DAHS 04H Mode Control 1 PLL1 05H Mode Control 2 FS2 06H DAC Control ...
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ASAHI KASEI „ Register Definitions Addr Register Name D7 00H Power Management 1 PMVCM R/W R/W Default 0 PMADL: ADC Lch Block Power Control 0: Power down (Default) 1: Power up When the PMADL or PMADR bit changes from “0” ...
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ASAHI KASEI PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are powered down. When all ...
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ASAHI KASEI Addr Register Name 02H Signal Select 1 MOGN R/W Default MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2) 0: OFF (Default When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs ...
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ASAHI KASEI DAHS DAC BPMSP BEEPM BPSSP BEEPL BEEPR MS0202-E-04 MOUT2 MIX ALC2 Figure 45. Speaker-amp switch control - 47 - [AK4537] ALCS SPK 2005/04 ...
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ASAHI KASEI Addr Register Name 03H Signal Select 2 DAHS R/W Default HPR: Rch of Headphone-Amp Power Control 0: Normal Operation 1: OFF(Default) HPL: Lch of Headphone-Amp Power Control 0: Normal Operation 1: OFF(Default) BPMHP: BEEPM to Headphone-amp Enable 0: ...
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ASAHI KASEI Addr Register Name 04H Mode Control 1 R/W Default DIF1-0: Audio Interface Format Select (see Table 13) 2 Default: “10” (ADC DAC: I BF: BICK frequency Select at Master Mode 0: 64fs (Default) 1: 32fs This ...
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ASAHI KASEI Addr Register Name 05H Mode Control 2 R/W Default SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and ...
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ASAHI KASEI Addr Register Name 06H DAC Control R/W Default DEM1-0: De-emphases response (see Table 16) Default: “01” (OFF) BST1-0: Select Low Frequency Boost Function (see Table 17) Default: “00” (OFF) DATTC: DAC Digital Attenuator Control Mode Select 0: Independent ...
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ASAHI KASEI Addr Register Name D7 07H MIC/HP Control R/W RD Default st MGAIN: 1 Mic-amp Gain control 0: 0dB 1: +20dB (Default) MSEL: Microphone select 0: Internal MIC (Default) 1: External MIC MICAD: Switch Control from Mic In to ...
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ASAHI KASEI Addr Register Name 08H Timer Select R/W Default LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (see Table 25) The IPGA value is changed immediately. When the IPGA value is changed continuously, the ...
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ASAHI KASEI Addr Register Name 09H ALC Mode Control 1 R/W Default LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be ...
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ASAHI KASEI ALC1: ALC1 Enable Flag 0: ALC1 Disable (Default) 1: ALC1 Enable ALC1 is enabled when ALC1 bit is “1”. Default is “0”(Disable). ALC2: ALC2 Enable Flag 0: ALC2 Disable 1: ALC2 Enable (Default) ALC2 is enabled after initialization ...
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ASAHI KASEI Addr Register Name 0BH Lch Input PGA Control 0FH Rch Input PGA Control R/W Default IPGAL6-0: Lch Input Analog PGA (see Table 32) IPGAR6-0: Rch Input Analog PGA (see Table 32) Default: “10H” (0dB) When IPGA gain is ...
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ASAHI KASEI Addr Register Name D7 0EH Volume Control ATTM R/W R/W Default 0 ATTS2-0: Attenuator select of signal from IPGA Lch to Stereo Mixer. (See Table 33) ATTS2-0 ATTM: Attenuator control for signal from IPGA Lch to Mono Mixer ...
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ASAHI KASEI Addr Register Name D7 10H Power Management 3 0 R/W RD Default 0 PMADR: ADC Rch Block Power Control 0: Power down (Default) 1: Power up When the PMADL or PMADR bit changes from “0” to “1”, the ...
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ASAHI KASEI Figure 47 shows the system connection diagram for the AK4537. An evaluation board [AKD4537] is available which demonstrates the optimum layout, power supply arrangements and measurement results MICOUT L 2 MICOUT ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4537 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD, PVDD and HVDD are supplied ...
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ASAHI KASEI „ Power up Upon power-up, bring the PDN pin = “L”. Initialize the internal registers to default values after the PDN pin = “H”. Set the following registers to establish the initial condition. Pow er Supply (2) PDN ...
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ASAHI KASEI „ Clock Set up When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied. 1. When X'tal is used in PLL mode. (Slave mode) MCKPD bit (Addr:01H, D7) (1) PMXTL bit ...
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ASAHI KASEI 2. When X'tal is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) PMXTL bit (Addr:01H, D6) 20ms(typ) (2) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) (3) PS1-0 bits 00 (Addr:04H, D5-4) MCKO pin BICK, ...
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ASAHI KASEI 3. When an external clock is used in PLL mode. (Slave mode) (1) MCKPD bit (Addr:01H, D7) (2) External MCLK (3) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) (4) MCKO pin BICK, LRCK (Slave Mode) PS1-0 bits ...
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ASAHI KASEI 4. When an external clock is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) (2) External MCLK (3) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) PS1-0 bits 00 (Addr:04H, D5-4) MCKO pin BICK, LRCK ...
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ASAHI KASEI „ MIC Input Recording (Mono) FS2-0 bits 000 (Addr:05H, D7-5) (1) MIC Control 00001 (Addr:07H, D2-0) (2) ALC1 Control 1 XXH (Addr:08H) (3) ALC1 Control 2 XXH (Addr:0AH) (4) ALC1 Control 3 XXH (Addr:09H) (5) ALC1 State ALC1 ...
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ASAHI KASEI „ Headphone-amp Output FS2-0 bits 000 (Addr:05H, D7-5) (1) BST1-0 bits 00 (Addr:06H, D3-2) (2) ATTL7-0 bits 0000000 (Addr:0CH 0DH, D7-0) (3) PMDAC bit (Addr:01H, D0) HPL/R bit (Addr:03H, D1-0) PMHPL/R bits (Addr:01H, D2-1) HPL/R pins External Mute ...
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ASAHI KASEI „ Speaker-amp Output FS2-0 bits 000 (Addr:05H, D7-5) (1) ALC2 bit 0 (Addr:09H, D6 (2) ATTL7-0 bits 0000000 (Addr:0CH 0DH, D7-0) (3) PMDAC bit (Addr:01H, D0) (4) PMSPK bit (Addr:01H, D3) SPPS bit (Addr:05H, D0) SPP pin Hi-Z ...
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ASAHI KASEI „ Stop of Clock MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”. 1. When X’tal is used in PLL mode (1) MCKO bit (Addr:03H, D4) PMXTL bit (Addr:01H, D6) (2) PMPLL bit (Addr:01H, D5) MCKPD bit (Addr:01H, D7) <Example> ...
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ASAHI KASEI 3. External clock mode r xtern <Example> (1) Pull down the XTI ...
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ASAHI KASEI 52pin QFN (Unit: mm) 7.2 ± 0.20 7.0 ± 0. 0.05 Note) The part of black at four corners on reverse side must not be soldered and must be open. „ Material & Lead ...
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... ASAHI KASEI XXXXXXX : MS0202-E-04 MARKING AKM AK4537VN XXXXXXX 1 Date code identifier (7 digits [AK4537] 2005/04 ...
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ASAHI KASEI Date (YY/MM/DD) Revision Reason 03/02/03 00 First Edition 03/03/24 01 Spec change: Error correct: 03/05/23 02 Error correct: MS0202-E-04 Revision History Page Contents 33 Headphone amp oscillation prevention circuit 0.22 F+10 10 20% resistor 5-6 Pin/Function NC pin: ...
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ASAHI KASEI Date (YY/MM/DD) Revision Reason 03/05/23 02 Explanation addition: MS0202-E-04 Page Contents 27 Manual Mode “When writing to IPGAR6-0 bits continually, the control register should be written by an interval more than zero crossing operation interval between IPGAL6-0 and ...
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ASAHI KASEI Date (YY/MM/DD) Revision Reason 03/05/23 02 Explanation addition: Explanation change: 04/11/26 03 Explanation addition: MS0202-E-04 Page Contents 55 Register Definitions (IPGAL6-0 and IPGAR6-0 bits) “When IPGA gain is changed, IPGAL6-0 and IPGAR6-0 bits should be written while PMMICL, ...
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ASAHI KASEI Date (YY/MM/DD) Revision Reason 05/04/27 04 Explanation change: These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor ...