AT90USB647 Atmel Corporation, AT90USB647 Datasheet - Page 147

• Manufacturer Part Number: AT90USB647
• Manufacturer: Atmel Corporation

Specifications of AT90USB647

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 48
• Ext Interrupts: 16
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 10
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3
7593K–AVR–11/09
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
7
–
R
0
7
–
R
0
7
–
R
0
(See “Interrupts” on page
(See “Interrupts” on page
(See “Interrupts” on page
6
–
R
0
6
–
R
0
6
–
R
0
68.) is executed when the TOVn Flag, located in TIFRn, is set.
5
ICIE3
R/W
0
5
ICF1
R/W
0
5
ICF3
R/W
0
68.) is executed when the ICFn Flag, located in TIFRn, is set.
4
–
R
0
4
–
R
0
4
–
R
0
68.) is executed when the OCFnC Flag, located in
68.) is executed when the OCFnB Flag, located in
68.) is executed when the OCFnA Flag, located in
3
OCIE3
C
R/W
0
3
OCF1C
R/W
0
3
OCF3C
R/W
0
2
OCIE3B
R/W
0
2
OCF1B
R/W
0
2
OCF3B
R/W
0
1
OCF1A
R/W
0
1
OCF3A
R/W
0
1
OCIE3A
R/W
0
AT90USB64/128
0
TOV1
R/W
0
0
TOV3
R/W
0
0
TOIE3
R/W
0
TIFR1
TIFR3
TIMSK3
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