ATmega168P

Manufacturer Part NumberATmega168P
ManufacturerAtmel Corporation
ATmega168P datasheets
 


Specifications of ATmega168P

Flash (kbytes)16 KbytesPin Count32
Max. Operating Frequency20 MHzCpu8-bit AVR
# Of Touch Channels16Hardware Qtouch AcquisitionNo
Max I/o Pins23Ext Interrupts24
Usb SpeedNoUsb InterfaceNo
Spi2Twi (i2c)1
Uart1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorYes
Crypto EngineNoSram (kbytes)1
Eeprom (bytes)512Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerYesTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers3Output Compare Channels6
Input Capture Channels1Pwm Channels6
32khz RtcYesCalibrated Rc OscillatorYes
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Features
High Performance, Low Power Atmel
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 4/8/16KBytes of In-System Self-Programmable Flash progam memory
– 256/512/512Bytes EEPROM
– 512/1K/1KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
®
QTouch
library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V for ATmega48P/88P/168PV
– 2.7 - 5.5V for ATmega48P/88P/168P
Temperature Range:
°
°
– -40
C to 85
C
Speed Grade:
– ATmega48P/88P/168PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega48P/88P/168P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V
Low Power Consumption at 1MHz, 1.8V, 25°C:
– Active Mode: 0.3mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.8µA (Including 32kHz RTC)
Note:
1. See
”Data Retention” on page 8
®
®
AVR
8-Bit Microcontroller
(1)
2
C compatible)
for details.
8-bit Atmel
Microcontroller
with 4/8/16K
Bytes In-System
Programmable
Flash
ATmega48P/V
ATmega88P/V
ATmega168P/V
Rev. 8025M–AVR–6/11

ATmega168P Summary of contents

  • Page 1

    ... Power-down Mode: 0.1µA – Power-save Mode: 0.8µA (Including 32kHz RTC) Note: 1. See ”Data Retention” on page 8 ® ® AVR 8-Bit Microcontroller ( compatible) for details. 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash ATmega48P/V ATmega88P/V ATmega168P/V Rev. 8025M–AVR–6/11 ...

  • Page 2

    Pin Configurations Figure 1-1. Pinout ATmega48P/88P/168P TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 ...

  • Page 3

    Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive ...

  • Page 4

    The various special features of Port D are elaborated in 86. 1.1 the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally CC connected to V through a low-pass filter. Note ...

  • Page 5

    Block Diagram Figure 2-1. Block Diagram Watchdog Watchdog Oscillator Oscillator Circuits / Generation EEPROM 8bit T/C 0 8bit T/C 2 USART 0 PORT D (8) 8025M–AVR–6/11 Power Timer Supervision POR / BOD & RESET Flash Clock 16bit T/C 1 ...

  • Page 6

    The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in ...

  • Page 7

    ... Comparison Between ATmega48P, ATmega88P and ATmega168P The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader sup- port, and interrupt vector sizes. sizes for the three devices. Table 2-1. Device ATmega48P ATmega88P ATmega168P ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism. ...

  • Page 8

    Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over ...

  • Page 9

    AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

  • Page 10

    ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...

  • Page 11

    Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and ...

  • Page 12

    General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...

  • Page 13

    The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...

  • Page 14

    SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is ...

  • Page 15

    ... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ATmega88P and ATmega168P” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...

  • Page 16

    Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); ...

  • Page 17

    ... For software security, the Flash Program memory space is divided into two sections, Boot Loader Section and Application Program Section in ATmega88P and ATmega168P. ATmega48P does not have separate Boot Loader and Application Program sec- tions, and the SPM instruction can be executed from the entire Flash. See SELFPRGEN ...

  • Page 18

    ... Figure 8-1. Figure 8-2. ATmega48P/88P/168P 18 Program Memory Map, ATmega48P Program Memory Application Flash Section Program Memory Map, ATmega88P and ATmega168P Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 8025M–AVR–6/11 ...

  • Page 19

    SRAM Data Memory Figure 8-3 The ATmega48P/88P/168P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...

  • Page 20

    Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 8-4. 8.4 EEPROM Data Memory The ATmega48P/88P/168P contains 256/512/512 bytes of data ...

  • Page 21

    Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. ...

  • Page 22

    Register Description 8.6.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:9 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • ...

  • Page 23

    ... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Support – Read-While-Write Self-Programming, ATmega88P and ATmega168P” on page 275 for details about Boot programming. ...

  • Page 24

    When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...

  • Page 25

    Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData 8025M–AVR–6/11 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out ...

  • Page 26

    The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...

  • Page 27

    System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

  • Page 28

    Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...

  • Page 29

    Table 9-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage ...

  • Page 30

    Figure 9-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL[3:1] as shown in on page Table 9-3. Frequency Range Notes: The ...

  • Page 31

    Table 9-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 9.4 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier ...

  • Page 32

    Figure 9-3. Table 9-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast ...

  • Page 33

    Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by ...

  • Page 34

    Table 9-10. CKSEL[3:0] 0100 0101 Note: 9.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See 29-1 ...

  • Page 35

    Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...

  • Page 36

    Table 9-16. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in ...

  • Page 37

    The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the ...

  • Page 38

    Register Description 9.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...

  • Page 39

    The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...

  • Page 40

    Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...

  • Page 41

    BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some ...

  • Page 42

    Power-down Mode When the SM[2:0] bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface address watch, ...

  • Page 43

    Power Reduction Register The Power Reduction Register (PRR), see vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...

  • Page 44

    Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the ...

  • Page 45

    Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, ...

  • Page 46

    Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A ...

  • Page 47

    ... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATmega168P, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48P and ATmega88P, the instruction placed at the Reset Vector must be an RJMP – ...

  • Page 48

    Figure 11-1. Reset Logic BODLEVEL [2..0] RSTDISBL 11.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used ...

  • Page 49

    Figure 11-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 11.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...

  • Page 50

    Figure 11-5. Brown-out Reset During Operation 11.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the ...

  • Page 51

    ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 11.8 Watchdog Timer 11.8.1 Features • Clocked from separate On-chip ...

  • Page 52

    To further ensure program security, altera- tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows the ...

  • Page 53

    Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. ...

  • Page 54

    The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds ...

  • Page 55

    Register Description 11.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused bits in ...

  • Page 56

    WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This ...

  • Page 57

    Table 11-2. WDP3 8025M–AVR–6/11 Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 512K (524288) cycles 1024K (1048576) cycles ...

  • Page 58

    ... Each Interrupt Vector occupies two instruction words in ATmega168P, and one instruction word in ATmega48P and ATmega88P. • ATmega48P does not have a separate Boot Loader Section. In ATmega88P and ATmega168P, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. 12.1 Interrupt Vectors in ATmega48P Table 12-1 ...

  • Page 59

    Table 12-1. Reset and Interrupt Vectors in ATmega48P (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48P is: Address Labels Code 0x000 ...

  • Page 60

    ... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see port – Read-While-Write Self-Programming, ATmega88P and ATmega168P” on page 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section ...

  • Page 61

    Table 12-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F ...

  • Page 62

    When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...

  • Page 63

    ... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see port – Read-While-Write Self-Programming, ATmega88P and ATmega168P” on page 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 8025M– ...

  • Page 64

    ... ATmega48P/88P/168P 64 shows reset and Interrupt Vectors placement for the various combina- Reset and Interrupt Vectors Placement in ATmega168P IVSEL Reset Address 0 0x000 1 0x000 0 Boot Reset Address 1 Boot Reset Address 1. The Boot Reset Address is shown in means unprogrammed while “ ...

  • Page 65

    ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168P is: Address Labels Code ...

  • Page 66

    ... Register Description 12.4.1 Moving Interrupts Between Application and Boot Space, ATmega88P and ATmega168P The MCU Control Register controls the placement of the Interrupt Vector table. 12.4.2 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...

  • Page 67

    Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...

  • Page 68

    External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[23:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[23:0] pins are configured as ...

  • Page 69

    Register Description 13.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused bits in ...

  • Page 70

    EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 1 – INT1: External Interrupt Request ...

  • Page 71

    PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt ...

  • Page 72

    Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), ...

  • Page 73

    I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

  • Page 74

    Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...

  • Page 75

    If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...

  • Page 76

    Figure 14-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

  • Page 77

    Assembly Code Example C Code Example unsigned char i; Note: 14.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save ...

  • Page 78

    Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...

  • Page 79

    Table 14-2 ure 14-5 on page 78 generated internally in the modules having the alternate function. Table 14-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for ...

  • Page 80

    Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port B, ...

  • Page 81

    AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis- connected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this ...

  • Page 82

    The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source. • ICP1/CLKO/PCINT0 – Port B, ...

  • Page 83

    Table 14-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 14.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-6. Port Pin 8025M–AVR–6/11 Overriding Signals for Alternate Functions ...

  • Page 84

    The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on ...

  • Page 85

    ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external ...

  • Page 86

    Table 14-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 14.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 ...

  • Page 87

    The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with ...

  • Page 88

    INT0/PCINT18 – Port D, Bit 2 INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source. • TXD/PCINT17 ...

  • Page 89

    Table 14-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8025M–AVR–6/11 PD3/OC2B/INT1/ PD2/INT0/ PCINT19 PCINT18 OC2B ENABLE 0 OC2B 0 INT1 ...

  • Page 90

    Register Description 14.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...

  • Page 91

    PORTD – The Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 14.4.9 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 14.4.10 PIND – The Port D Input Pins Address Bit 0x09 ...

  • Page 92

    Timer/Counter0 with PWM 15.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...

  • Page 93

    Figure 15-1. 8-bit Timer/Counter Block Diagram 15.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output ...

  • Page 94

    The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The ...

  • Page 95

    The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the ...

  • Page 96

    The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR0x ...

  • Page 97

    Figure 15-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) ...

  • Page 98

    Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...

  • Page 99

    The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...

  • Page 100

    In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to ...

  • Page 101

    Figure 15-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...

  • Page 102

    BOTTOM the OCnx value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the Compare ...

  • Page 103

    Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 PWM mode where OCR0A is TOP. Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk ...

  • Page 104

    Register Description 15.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

  • Page 105

    Table 15-4 rect PWM mode. Table 15-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...

  • Page 106

    Table 15-7 rect PWM mode. Table 15-7. COM0B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation ...

  • Page 107

    TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...

  • Page 108

    Table 15-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

  • Page 109

    TIMSK0 – Timer/Counter Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match ...

  • Page 110

    Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...

  • Page 111

    Timer/Counter1 with PWM 16.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer ...

  • Page 112

    Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

  • Page 113

    Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...

  • Page 114

    Assembly Code Examples ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples unsigned int i; ... /* Set TCNT1 to 0x01FF */ ...

  • Page 115

    Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of ...

  • Page 116

    Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example void TIM16_WriteTCNT1( unsigned int i ...

  • Page 117

    Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

  • Page 118

    The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...

  • Page 119

    TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...

  • Page 120

    I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously compares ...

  • Page 121

    PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...

  • Page 122

    Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...

  • Page 123

    PWM refer to page 133. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. ...

  • Page 124

    Figure 16-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...

  • Page 125

    The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...

  • Page 126

    When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...

  • Page 127

    OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

  • Page 128

    TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...

  • Page 129

    OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...

  • Page 130

    Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...

  • Page 131

    Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 16-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...

  • Page 132

    Figure 16-13 Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • ...

  • Page 133

    Table 16-2 PWM mode. Table 16-2. COM1A1/COM1B1 Note: Table 16-3 correct or the phase and frequency correct, PWM mode. Table 16-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B ...

  • Page 134

    Table 16-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

  • Page 135

    When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...

  • Page 136

    TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure ...

  • Page 137

    ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...

  • Page 138

    TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input ...

  • Page 139

    Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 92 111 share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source ...

  • Page 140

    Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...

  • Page 141

    Register Description 17.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...

  • Page 142

    Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and ...

  • Page 143

    Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...

  • Page 144

    Figure 18-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...

  • Page 145

    Figure 18-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...

  • Page 146

    The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...

  • Page 147

    Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...

  • Page 148

    Figure 18-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

  • Page 149

    In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...

  • Page 150

    OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase Correct PWM Mode ...

  • Page 151

    COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for ...

  • Page 152

    Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 18-10 Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 18-11 Figure 18-11. Timer/Counter Timing Diagram, Clear ...

  • Page 153

    Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching ...

  • Page 154

    Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, ...

  • Page 155

    When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for ...

  • Page 156

    Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the ...

  • Page 157

    Table 18-4 rect PWM mode. Table 18-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits ...

  • Page 158

    Note: Table 18-7 rect PWM mode. Table 18-7. COM2B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bits 1:0 – WGM21:0: Waveform ...

  • Page 159

    TCCR2B – Timer/Counter Control Register B Bit (0xB1) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with ...

  • Page 160

    Table 18-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

  • Page 161

    TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is ...

  • Page 162

    ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value • Bit 7 – RES: Reserved bit This bit is reserved and will always read as zero. • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is ...

  • Page 163

    The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 18.11.9 GTCCR – ...

  • Page 164

    SPI – Serial Peripheral Interface 19.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...

  • Page 165

    The interconnection between Master and Slave CPUs with SPI is shown in 165. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin ...

  • Page 166

    When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to ”Alternate Port Functions” on page Table 19-1. Pin MOSI MISO SCK SS Note: The following code examples show how to ...

  • Page 167

    Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8025M–AVR–6/11 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...

  • Page 168

    The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...

  • Page 169

    SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...

  • Page 170

    Figure 19-3. SPI Transfer Format with CPHA = 0 Figure 19-4. SPI Transfer Format with CPHA = 1 ATmega48P/88P/168P 170 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE ...

  • Page 171

    Register Description 19.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...

  • Page 172

    Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...

  • Page 173

    SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...

  • Page 174

    USART0 20.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

  • Page 175

    Figure 20-1. USART Block Diagram Note: 20.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave ...

  • Page 176

    Figure 20-2 Figure 20-2. Clock Generation Logic, Block Diagram DDR_XCKn Signal description: txclk rxclk xcki operation. xcko fosc 20.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes ...

  • Page 177

    Table 20-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f ...

  • Page 178

    External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...

  • Page 179

    A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...

  • Page 180

    USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...

  • Page 181

    For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) ...

  • Page 182

    XCKn pin will be overridden and used as transmission clock. 20.6.1 Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data ...

  • Page 183

    For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } ...

  • Page 184

    UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit ...

  • Page 185

    UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: ...

  • Page 186

    Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer error, return -1 andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn) breq USART_ReceiveNoError ldi ldi ...

  • Page 187

    Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

  • Page 188

    The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...

  • Page 189

    Figure 20-5. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the ...

  • Page 190

    Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop ...

  • Page 191

    Table 20-2. # (Data+Parity Bit) Table 20-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

  • Page 192

    When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...

  • Page 193

    Register Description 20.10.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...

  • Page 194

    Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the ...

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    Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...

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    Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...

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    Table 20-8. UCPOLn 0 1 20.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be ...

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    Table 20-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 ...

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    Table 20-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

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    Table 20-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...