ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 306

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.16.5
25.16.6
8077H–AVR–12/09
PRESCALER - ADC Clock Prescaler register
INTFLAGS - ADC Interrupt Flag register
• Bits 7:3 - Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bits 2:0 - PRESCALER[2:0]: ADC Prescaler configuration
These bits define the ADC clock relative to the Peripheral clock, according to
page
Table 25-7.
• Bits 7:4 - Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bits 3:0 - CH[3:0]IF: Interrupt flags
These flags are set when the ADC conversion is complete for the corresponding ADC channel. If
an ADC channel is configured for compare mode, the corresponding flag will be set if the com-
pare condition is met. CHnIF is automatically cleared when the ADC channel n interrupt vector is
executed. The flag can also be cleared by writing a one to its bit location.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
PRESCALER[2:0]
306.
000
001
010
011
100
101
110
111
R
R
7
0
7
0
-
-
ADC Prescaler settings
R
6
0
-
R
6
0
-
Group Configuration
R
5
0
-
R
5
0
-
DIV128
DIV256
DIV512
DIV16
DIV32
DIV64
DIV4
DIV8
R
4
0
-
R
4
0
-
R
3
0
-
R/W
3
0
R/W
2
0
R/W
System clock division factor
2
0
CH[3:0]IF
PRESCALER[2:0]
R/W
1
0
R/W
1
0
128
256
512
16
32
64
4
8
XMEGA A
R/W
0
0
R/W
0
0
Table 25-7 on
PRESCALER
INTFLAGS
306