ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 81

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6
7.7
8077H–AVR–12/09
PLL with 1-31x Multiplication Factor
DFLL 2 MHz and DFLL 32 MHz
The System Clock selection and prescaler registers are protected by the Configuration Change
Protection mechanism, employing a timed write procedure for changing the system clock and
prescaler settings. For details refer to
A built-in Phase Locked Loop (PLL) can be used to generate a high frequency system clock. The
PLL has a user selectable multiplication factor from 1 to 31. The output frequency, f
by the input frequency, f
a minimum output frequency of 10 MHz.
Four different reference clock sources can be chosen as input to the PLL:
To enable the PLL the following procedure must be followed:
1.Enable clock reference source.
2.Set the multiplication factor and select the clock reference for the PLL.
3.Wait until the clock reference source is stable.
4.Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The
PLL must be disabled before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stabile and the PLL has
locked.
If using PLL and DFLL the active reference cannot be disabled.
Two built-in Digital Frequency Locked Loops (DFLLs) can be used to improve the accuracy of
the 2 MHz and 32 MHz internal oscillators. The DFLL compares the oscillator frequency with a
more accurate reference clock to do automatic run-time calibration of the oscillator. The choices
for the reference clock sources are:
The DFLLs divide the reference clock by 32 to use a 1.024 kHz reference. The reference clock is
individually selected for each DFLL as shown on
• 2 MHz internal oscillator
• 32 MHz internal oscillator divided by 4
• 0.4 - 16 MHz Crystal Oscillator
• External clock
• 32.768 kHz Calibrated Internal Oscillator
• 32.768 kHz Crystal Oscillator connected to the TOSC pins
IN
multiplied with the multiplication factor, PLL_FAC. The PLL must have
”Configuration Change Protection” on page
f
OUT
=
f
IN
⋅
Figure 7-6 on page
PLL_FAC
82.
XMEGA A
12.
OUT
is given
81