ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 49

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. DMA - Direct Memory Access Controller
5.1
5.2
8077H–AVR–12/09
Features
Overview
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The XMEGA Direct Memory Access (DMA) Controller is a highly flexible DMA Controller capable
of transferring data between memories and peripherals with minimal CPU intervention. The
DMA controller has flexible channel priority selection, several addressing modes, double buffer-
ing capabilities and large block sizes.
The DMA Controller can move data between memories and peripherals, between memories and
between peripheral registers directly.
There are four DMA channels that have individual source, destination, triggers and block sizes.
The different channels also have individual control settings and individual interrupt settings and
interrupt vectors. Interrupt requests may be generated both when a transaction is complete or if
the DMA Controller detects an error on a DMA channel. When a DMA channel requests a data
transfer, the bus arbiter will wait until the AVR CPU is not using the data bus and permit the DMA
Controller to transfer data. Transfers are done in bursts of 1, 2, 4 or 8 bytes. Addressing can be
static, incremental or decremental. Automatic reload of source and/or destination address can
be done after each burst transfer, block transfer, when transmission is complete, or disabled.
Both application software, peripherals and Events can trigger DMA transfers.
The DMA Controller allows high-speed transfers with minimal CPU intervention
Four DMA Channels with separate
From 1 byte to 16M bytes data transfer in a single transaction
Up to 64 KByte block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Internal and external transfer triggers
Multiple addressing modes
Optional reload of source and destination address at the end of each
Optional Interrupt on end of transaction
Programmable channel priority
– from one memory area to another
– from memory area to peripheral
– from peripheral to memory area
– from peripheral to another peripheral
– transfer triggers
– interrupt vectors
– addressing modes
– Static
– Increment
– Decrement
– Burst
– Block
– Transaction
XMEGA A
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