ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 313

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.17.4
25.17.5
25.17.5.1
25.17.5.2
8077H–AVR–12/09
INTFLAGS - ADC Channel Interrupt Flag registers
RESH - ADC Channel n Result register High
12-bit mode, left adjusted
12-bit mode, right adjusted
• Bits 1:0 – INTLVL[1:0]: ADC Interrupt Priority Level and Enable
These bits enable the ADC channel interrupt and select the interrupt level as described in
tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
interrupt will be triggered when the IF in the INTFLAGS register is set.
• Bits 7:1 – Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 – IF: ADC Channel Interrupt Flag
The interrupt flag is set when the ADC conversion is complete. If the channel is configured for
compare mode, the flag will be set if the compare condition is met. IF is automatically cleared
when the ADC channel interrupt vector is executed. The bit can also be cleared by writing a one
to the bit location.
For all result registers and with any ADC result resolution, a signed number is represented in 2’s
complement form and the MSB represents the sign bit.
The RESL and RESH register pair represents the 16-bit value ADCRESULT. Reading and writ-
ing 16-bit values require special attention, refer to
page 12
• Bits 7:0 - RES[11:4]: ADC Channel Result, high byte
These are the 8 MSB of the 12-bit ADC result.
• Bits 7:4 - Reserved
These bits will in practice be the extension of the sign bit CHRES11 when ADC works in differen-
tial mode and set to zero when ADC works in signed mode.
• Bits 3:0 - RES[11:8]: ADC Channel Result, high byte
These are the 4 MSB of the 12-bit ADC result.
Bit
+0x03
Read/Write
Initial Value
12-bit, left.
12-bit, right
8-bit
for details.
Bit
+0x05
Read/Write
Initial Value
R
7
0
-
R
6
0
-
R
7
0
-
-
R
0
5
-
R
6
0
-
-
R
4
0
-
R
5
0
-
-
Section 3.11 ”Accessing 16-bits Registers” on
R
3
0
-
R
4
0
-
-
RES[11:4]
R
2
0
-
R
3
0
-
R
1
0
R
-
2
0
-
RES[11:8]
XMEGA A
123. The enabled
R/W
IF
0
0
R
1
0
-
INTFLAGS
R
0
0
-
Sec-
313