ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 245

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13 Register Description – USB
20.13.1
20.13.2
8331A–AVR–07/11
CTRLA – Control Register A
CTRLB – Control Register B
• Bit 7 – ENABLE: USB Enable
Setting this bit enables the USB interface. Clearing this bit disables the USB interface, and
immediately aborts any ongoing transactions.
• Bit 6 – SPEED: Speed Select
This bit selects between low and full speed operation. By default this bit is zero and low speed
operation is selected. Setting this bit enables full speed operation.
• Bit 5 – FIFOEN: USB FIFO Enable
Setting this bit enables the USB Transaction Complete FIFO (FIFO), and the FIFO stores the
endpoint configuration table address of each endpoint that generates a transaction complete
interrupt. Clearing this bit disables the FIFO, and frees the allocated SRAM memory.
• Bit 4 – STFRNUM: Store Frame Number Enable
Setting this bit enables storing of the last SOF token frame number in the Frame Number (FRA-
MENUM) register. Clearing this bit disables the function.
• Bit 3:0 – MAXEP[3:0]: Maximum Endpoints Address
These bits select the number of endpoint addresses used by the USB module. Incoming packets
with a higher endpoint number than this address will be discarded. Packets with endpoint
address lower than or equal to this address will cause the USB module to look up the addressed
endpoint in the endpoint configuration table.
Bit
+0x01
Read/Write
Initial Value
• Bit 7:5 – Reserved
These bits are reserved for future use. For compatibility with future devices, always write these
bits to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
ENABLE
R
7
–
0
R/W
7
0
SPEED
R
6
–
0
R/W
6
0
FIFOEN
5
–
R
0
R/W
5
0
PULLRST
R/W
STFRNUM
4
0
R/W
4
0
R
3
–
0
Atmel AVR XMEGA AU
R/W
3
0
RWAKEUP
R/W
2
0
R/W
2
0
MAXEP[3:0]
GNACK
R/W
R/W
1
0
1
0
ATTACH
R/W
R/W
0
0
0
0
CTRLA
CTRLB
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