ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 98

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.10.6
7.10.7
8331A–AVR–07/11
PLLCTRL – PLL Control Register
DFLLCTRL – DFLL Control Register
• Bit 7:6 – PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to
Table 7-9.
Notes:
• Bit 5 – PLLDIV: PLL Divided Output Enable
Setting this bit will divide the output from the PLL by 2.
• Bit 4:0 – PLLFAC[4:0]: Multiplication Factor
These bits select the multiplication factor for the PLL. The multiplication factor can be in the
range of from 1x to 31x.
• Bit 7:3 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2:1 – RC32MCREF[1:0]: 32MHz Oscillator Calibration Reference
These bits are used to select the calibration source for the 32MHz DFLL according to the
7-10 on page
Bit
+0x06
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
PLLSRC[1:0]
1. The 32.768kHz TOSC cannot be selected as the source for the PLL. An external clock must be
a minimum 0.4MHz to be used as the source clock.
00
01
10
11
R
7
–
0
99. These bits will select only which calibration source to use for the DFLL. In addi-
PLL Clock Source
R/W
7
0
PLLSRC[1:0]
R
6
–
0
R/W
6
0
Group Configuration
R
5
–
0
PLLDIV
R/W
RC32M
5
0
RC2M
XOSC
—
4
–
R
0
R/W
4
0
R
3
–
0
Atmel AVR XMEGA AU
PLL Input Source
2MHz internal oscillator
Reserved
32MHz internal oscillator
External clock source
R/W
3
0
R/W
PLLFAC[4:0]
2
0
RC32MCREF[1:0]
R/W
2
0
Table 7-9 on page
R/W
1
0
R/W
(1)
1
0
RC2MCREF
R/W
0
0
R/W
0
0
98.
DFLLCTRL
PLLCTRL
Table
98