ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 487

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8331A–AVR–07/11
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
** NOP is only inserted for CAS3
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
Clk
CS
CLK
CKE
WE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
PER2
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
** NOP is only inserted for CAS3
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
Clk
CS
CLK
CKE
WE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
PER2
Burst access within a single page
Burst access crossing page boundary
Row Adr
Row Adr
Figure 36-50. Burst access within a single page
Figure 36-51. Burst access crossing page boundary
Col Adr
Col Adr
D[3:0]
Bank Adr
D[3:0]
D[7:4]
D[7:4]
Bank Adr
Col Adr
D[3:0]
Col Adr
D[3:0]
D[7:4]
0x400
0x0
D[7:4]
Atmel AVR XMEGA AU
Bank Adr
Col Adr
Col Adr
D[3:0]
D[3:0]
D[7:4]
D[7:4]
0x400
0x0
0x400
0x0
487