SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 176

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

10.20.9
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SAM3S8/SD8
SAM3S8/SD8
System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have
configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in
their attributes.
The system fault handlers and the priority field and register for each handler are:
Table 10-32. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and
bits[3:0] read as zero and ignore writes.
Handler
Memory management
fault
Bus fault
Usage fault
SVCall
PendSV
SysTick
Field
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
“System Handler Priority Register 1” on page 177
“System Handler Priority Register 2” on page 178
“System Handler Priority Register 3” on page 178
Register description
Table 10-30 on page 164
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
for